ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 166

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

13. Timer/Counter Prescaler
13.1
13.2
114
Prescaler Reset
External Clock Source
ATtiny24/44/84
Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counters. Tn
is used as a general name, n = 0, 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for
situations where a prescaled clock is used. One example of prescaling artifacts occurs when the
timer is enabled and clocked by the prescaler (CSn2:0 = 2, 3, 4, or 5). The number of system
clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-
tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
shows a functional equivalent block diagram of the Tn synchronization and edge detector logic.
The registers are clocked at the positive edge of the internal system clock (
transparent in the high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects.
Figure 13-1. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
CLK_I/O
Tn
clk
I/O
/1024.
D
LE
CLK_I/O
Q
). Alternatively, one of four taps from the prescaler can be used as a
Synchronization
D
Q
T
0
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
CLK_I/O
D
Q
/8, f
Figure 13-1 on page 114
CLK_I/O
Edge Detector
/64, f
clk
I/O
). The latch is
8006G–AVR–01/08
CLK_I/O
Tn_sync
(To Clock
Select Logic)
Tn
/256, or
). The