ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 68

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

5.2.1
5.3
16
EEPROM Data Memory
ATtiny24/44/84
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny24/44/84 are all accessible through all these addressing modes.
The Register File is described in
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
16.
Figure 5-3.
The ATtiny24/44/84 contains 128/256/512 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register. For a detailed description of Serial data
downloading to the EEPROM, see
Data Memory Map
On-chip Data SRAM Access Cycles
Address
clk
Data
Data
WR
CPU
RD
(128/256/512 x 8)
64 I/O Registers
Data Memory
Internal SRAM
Compute Address
32 Registers
“General Purpose Register File” on page
T1
Memory Access Instruction
“Serial Downloading” on page
0x0DF/0x015F/0x025F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Address valid
CPU
T2
cycles as described in
Next Instruction
163.
T3
10.
Figure 5-3 on page
8006G–AVR–01/08