MAX11040 Maxim Integrated Products, MAX11040 Datasheet - Page 9

• Manufacturer Part Number: MAX11040
• Description: Sigma-Delta ADC
• Manufacturer: Maxim Integrated Products

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PIN
16
17
18
19
20
21
22
23
24
25
26
30
32
33
34
36
37
38
DRDYOUT
OVRFLW
CLKOUT
DRDYIN
FAULT
NAME
AIN3+
AIN2+
DOUT
AVDD
SCLK
SYNC
XOUT
AIN3-
AIN2-
REF3
REF2
DIN
XIN
_______________________________________________________________________________________
Serial-Clock Input. Clocks in data at DIN on the falling edge of SCLK and clocks out data at DOUT on the
rising edge of SCLK.
Serial Data Input. Data at DIN is clocked in on the falling edge of SCLK.
Serial Data Output. The drive for DOUT is enabled by a falling edge on CS while CASCIN is low or by a
falling edge on CASCIN while CS is low. DOUT is disabled/three-stated when CS is high or after the
appropriate number of data bytes have been transferred in response to the requested command. Data is
clocked out at DOUT on the rising edge of SCLK.
Acti ve- Low O ver vol tag e Faul t Ind i cator O utp ut. F AU LT g oes l ow w hen any anal og i np ut g oes outsi d e the faul t
thr eshol d r ang e ( b etw een V
r esi stor , al l ow i ng w i r e- N OR functi onal i ty. S ee the Anal og Inp ut O ver vol tag e and Faul t P r otecti on secti on.
Active-Low Channel Data Overflow Output. OVRFLW goes low when a conversion result goes outside the
voltage range bounded by the positive and negative full scale on one or more of the analog input
channels or when FAULT goes low. The OVRFLW output is open drain with a 30kΩ internal pullup resistor,
allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
Buffered Clock Output. When the XTALEN bit in the configuration register is 1 and a crystal is installed
between XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator’s clock. Setting the
XTALEN bit to 0 places CLKOUT in a high-impedance state.
Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the
availability of a new conversion result. DRDYOUT transitions high at the next CS falling edge or when
DRDYIN = 1. See the Multiple Device Connection section.
Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high. When
DRDYIN = 0, DRDYOUT outputs a logic-low when a new conversion result is available. See the Multiple
Device Connection section. Connect DRDYIN to DGND when not daisy chaining multiple devices.
Sampling Synchronization Input. The falling edge of SYNC aligns sampling and output data so that
multiple devices sample simultaneously. Synchronize multiple devices running from independent crystals
by connecting DRDYOUT of the last device in the chain to the SYNC inputs of all devices in the chain.
Connect SYNC to DGND for single device operation. See the Multiple Device Connection section.
Crystal Oscillator Output. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator. Leave XOUT unconnected when driving the MAX11040 with an external
frequency. See the Crystal Oscillator section.
Crystal Oscillator/Clock Input. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator or drive XIN with an external clock and leave XOUT unconnected. See
the Crystal Oscillator section.
Positive Analog Supply Voltage. Bypass to AGND with a 1µF capacitor in parallel with a 0.01µF capacitor
as close as possible to the device.
ADC3 Buffered Reference Voltage. Bypass with a 1µF capacitor to AGND.
Positive Analog Input Channel 3
Negative Analog Input Channel 3
ADC2 Buffered Reference Voltage. Bypass with a 1µF capacitor to AGND.
Positive Analog Input Channel 2
Negative Analog Input Channel 2
24-Bit, 4-Channel, Simultaneous-Sampling,
P FT
and V
Cascadable, Sigma-Delta ADC
N FT
) . The F AU LT outp ut i s op en d r ai n w i th a 30kΩ i nter nal p ul l up
FUNCTION
Pin Description (continued)
9