MAX11040 Maxim Integrated Products, MAX11040 Datasheet - Page 11

• Manufacturer Part Number: MAX11040
• Description: Sigma-Delta ADC
• Manufacturer: Maxim Integrated Products

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Table 1. Bandwidth vs. Output Data Rate
The MAX11040 contains an on-chip digital lowpass fil-
ter that processes the data stream from each modulator
and generates the high-resolution output data. The low-
pass filter frequency response is determined by the
programmable output data rate. At the nominal 16ksps
output data rate, the -3dB bandwidth of the filter is
3.4kHz. The passband flatness is better than ±0.1dB
from 0 to 1.74kHz. The notches are located at 5.75kHz
and 7.195kHz. These frequencies scale linearly with the
output data rate. See Figure 2 and Table 1 for the fre-
quency response at different data rates.
Figure 2. Digital Filter Response
OUTPUT DATA
RATE (ksps)
0.5
10
12
16
32
64
1
2
4
8
-1
-2
-3
-4
-5
-6
1
0
0
-3dB BANDWIDTH
0.4
______________________________________________________________________________________
0.8
(kHz)
24-Bit, 4-Channel, Simultaneous-Sampling,
0.11
0.21
0.42
0.85
1.69
2.11
2.54
3.38
6.78
13.5
f
0.12
AIN
/f
SAMPLE
0.16
0.20
-0.1dB BANDWIDTH
0.24
Digital Filter
0.28
(kHz)
0.05
0.11
0.22
0.43
0.87
1.09
1.31
1.74
3.48
6.96
Cascadable, Sigma-Delta ADC
Since the transfer function of a digital filter is repeatable
and predictable, it is possible to correct for frequency-
dependent attenuation in downstream software. See
the Compensating for the Rolloff of the Digital Filter in a
Typical FFT Analysis section. The transfer function is
defined by the following equation:
where:
The digital filter determines the latency of the
MAX11040. Latency is defined as the time between the
effective point in time that a sample is taken and when
the resulting digital data is available for reading.
The latency of the converter is specified by the follow-
ing equation:
where t
programmed sample rate), determined by f
and the selected output data rate, and PHI is the pro-
grammed sampling instant delay for the channel in
question (0 ≤ PHI ≤ 255). The latency is approximately
405µs at 16ksps.
Gain f
Gain is the filter gain.
f
f
nally 16kHz.
f
24.576MHz.
FIR_Gain (f
ter with the following filter coefficients, as a function
of the analog input frequency f
cients are applied at the output data rate:
AIN
SAMPLE
XINCLOCK
Latency = (6 x t
(
AIN
DOUT
+ 0.021484375
+ 0.304687500
+ 0.539062500
+ 0.304687500
+ 0.021484375
- 0.072265625
- 0.035156250
- 0.035156250
- 0.072265625
is the analog input frequency.
)
=
is the programmed output data rate, nomi-
⎛
⎜
⎜
⎜
⎜ ⎜
⎝
is the data output period (inverse of the
sin
AIN
is the clock frequency at XIN, nominally
sin
⎛
⎜
⎝
π
) is the normalized gain of the FIR fil-
⎛
⎜
⎝
π
×
DOUT
×
f
XINCLOCK
f
SAMPLE
f
f
AIN
AIN
) + (PHI x 1.3µs) + 30µs
⎞
⎟
⎠
⎞
⎟
⎠
⎞
⎟
⎟
⎟
⎟ ⎟
⎠
3
(
AIN
FIR Gain f
. These coeffi-
_
XINCLOCK
Latency
(
AIN
)
)
11