MAX11040 Maxim Integrated Products, MAX11040 Datasheet - Page 20

• Manufacturer Part Number: MAX11040
• Description: Sigma-Delta ADC
• Manufacturer: Maxim Integrated Products

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Table 7. Data Rate Control Register
Table 8. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0]
24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
20
FSAMPC[2:0]
[15:13]
[12:11]
[10:0]
BITS
______________________________________________________________________________________
001
010
011
FSAMPF[10:0]
FSAMPC[2:0]
Don’t Care
NAME
FSAMPF[10:0]
10111111111
00000000001
00000000000
10111111111
00000000001
00000000000
10111111111
00000000001
00000000000
11xxxxxxxxx
11xxxxxxxxx
11xxxxxxxxx
Output data rate coarse adjust bits. FSAMPC[2:0] sets the coarse cycle factor.
Don’t-care bits.
Output data rate fine adjust bits. FSAMPF[10:0] increases the output data period by a number of
XIN clock cycles. This number is the value of the register times the fine cycle factor. Values of
FSAMPF greater than 1535 have no additional effect.
FSAMPC
FSAMPC
OUTPUT DATA
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
RATE (sps)
1000.0
1000.3
1000.3
1998.7
2000.0
250.1
250.1
499.7
500.0
500.2
500.2
999.3
Coarse Cycle
Factor
128
64
32
16
(24.576MHz CLOCK CYCLES)
4
8
2
1
OUTPUT DATA PERIOD
98272
98272
49184
49152
49136
49136
24592
24576
24568
24568
12296
12288
DESCRIPTION
XIN Fine Cycle Factor
32 cycles
16 cycles
1/2 cycle
1/4 cycle
8 cycles
4 cycles
2 cycles
1 cycle
(f
XIN CLOCK
Sample Rate in ksps
FSAMPF OUTPUT DATA PERIOD
(24.576MHz CLOCK CYCLES)
0.5
16
32
64
= 24.576MHz)
1
2
4
8
RESOLUTION
32
16
8