MAX11040 Maxim Integrated Products, MAX11040 Datasheet - Page 10

• Manufacturer Part Number: MAX11040
• Description: Sigma-Delta ADC
• Manufacturer: Maxim Integrated Products

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The MAX11040 is a 24-bit, simultaneous-sampling,
4-channel, sigma-delta ADC including support for syn-
chronized sampling and daisy chaining of the serial
interface across multiple (up to eight) MAX11040
devices. The serial interface of the set of synchronized
devices behaves as one device. Each channel includes
a differential analog input, a sigma-delta modulator, a
digital decimation filter, an independent programmable
sampling delay, and a buffered reference signal from
the internal or an external reference. The device con-
tains an internal crystal oscillator. The output data rate,
24-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADC
10
AIN0+
AIN1+
AIN2+
AIN3+
AIN0-
AIN1-
AIN2-
AIN3-
1μF
1μF
1μF
1μF
1μF
______________________________________________________________________________________
AIN0+
AIN0-
REF0
AIN1+
AIN1-
REF1
AIN2+
AIN2-
REF2
AIN3+
AIN3-
REF3
REFIO
0.01μF
1μF
AGND
Typical Operating Circuit
AVDD
3.3V
MAX11040
Detailed Description
DVDD
3.3V
DGND
CASCOUT
DRDYOUT
0.01μF
OVRFLW
CLKOUT
CASCIN
DRDYIN
1μF
FAULT
XOUT
DOUT
SYNC
SCLK
DIN
XIN
CS
24.576MHz
MICROCONTROLLER
20pF
20pF
OR DSP
the effective sample rate of the ADC, is software pro-
grammable.
The MAX11040 operates from a single 3.0V to 3.6V
analog supply and a 2.7V to V
4-wire serial interface is SPI/QSPI/MICROWIRE and
DSP compatible.
Each channel of the MAX11040 performs analog-to-
digital conversion on its input using a dedicated
switched-capacitor sigma-delta modulator. The modula-
tor converts the input signal into low-resolution digital data
for which the average value represents the digitized sig-
nal information at 3.072Msps for a 24.576MHz XIN clock.
This data stream is then presented to the digital filter for
processing to remove the high-frequency noise that cre-
ates a high-resolution 24-bit output data stream.
The input sampling network of the analog input consists
of a pair of 4pF capacitors (C
plates of which are connected to AIN_+ and AIN_- dur-
ing the track phase and then shorted together during
the hold phase (see Figure 1). The internal switches
have a total series resistance of 400Ω. Given a
24.576MHz XIN clock, the switching frequency is
3.072MHz. The sampling phase lasts for 120ns.
Figure 1. Simplified Track/Hold Stage
AIN_+
AIN_-
HOLD
TRACK
TRACK
MAX11040
C
C
SAMPLE+
SAMPLE-
R
AVDD
ON
SAMPLE
AVDD/2
ADC Modulator
digital supply. The
TO ADC
R
), the bottom
ON