CY3138R62 Cypress Semiconductor Corp., CY3138R62 Datasheet - Page 4

• Manufacturer Part Number: CY3138R62
• Description: Warp Enterprise Verilog PC
• Manufacturer: Cypress Semiconductor Corp.

All of the design-entry methods described can be mixed as
desired so long as only one HDL is used. Verilog have the
ability to combine both high- and low-level entry methods in a
single file. The flexibility and power of Verilog allow users of
Warp Enterprise to describe designs using whatever method is
appropriate for their particular design.
Finite State Machine Editor
Aldec’s Active-HDL™ FSM finite state machine editor, allows
graphic design entry through the use of graphical state dia-
grams. A design may be represented graphically using state
diagrams and data flow logic. This tool will automatically
generate the HDL code of the design.
HDL Block Diagram Editor
The HDL block diagram editor lets you represent portions of
your code with graphical symbols. This representation allows
you to view the high-level structure of your complex designs
and lets you copy and paste entire modules of your design
within or between designs. The editor comes with a library of
HDL blocks optimized for Cypress devices. Warp Enterprise
comes with utility that converts HDL text into these blocks.
Language Assistant
The language assistant is a library of language templates that
you can browse and automatically insert into your HDL text.
They provide syntax and structure and give examples to aid
users who are new using a particular HDL.
Flow Manager
The flow manager is a special interface that helps you keep
track of your complex projects. It arranges the tools as part of
the logical flow the designer takes through a project and re-
members what steps have been completed on which designs.
Source-Level Simulation
Warp Enterprise’s source-level behavioral simulator helps you
catch problems with your code early in the design process by
letting you simulate a design before synthesis. The tool lets
you graphically watch inputs and outputs, gives you timing in-
formation and allows you to step through your code line by line.
Compilation
Once the Verilog description of the design is complete, it is
compiled using Warp Enterprise. Although implementation is with
a single command, compilation is actually a multistep process as
shown in Figure 1. The first part of the compilation process is the
Document #: 38-03045 Rev. *A
Figure 3. Three-Bit Shift Register Circuit Design
clk
x
d
clk
q
q0
d
clk
q
q1
d
clk
q
q2
same for all devices. The input description is synthesized to a logical
representation of the design. Warp synthesis is unique in that the
input languages support device-independent design descriptions.
Competing programmable logic compilers require very specific and
device-dependent information in the design description.
Warp synthesis is based on UltraGen technology. This tech-
nology allows Warp Enterprise to infer adders, subtractors,
multipliers, comparators, counters and shifters from the be-
havioral descriptions. Warp Enterprise then replaces these op-
erators internally with an architecture-specific circuit. This cir-
cuit or “module” is also pre-optimized for either area or speed.
Warp Enterprise uses the appropriate implementation based
on user directives.
The second step of compilation is an iterative process of opti-
mizing the design and fitting the logic into the targeted device.
Logical optimization in Warp Enterprise is accomplished using
Espresso algorithms. The optimized design is automatically fed to
the Warp Enterprise fitter for targeting a PLD or CPLD. This fitter
supports the automatic or manual placement of pin assignments as
well as automatic selection of D or T flip-flops. After optimization and
fitting, Warp Enterprise creates a JEDEC or Intel hex file for the
specified PLD or CPLD.
Automatic Error Tracking
Warp Enterprise features automatic error location that allows
problems to be diagnosed and corrected in seconds. Errors
from compilation are displayed immediately in a window. If the
user highlights a particular error, Warp Enterprise will automat-
ically open the source code file and highlight the offending line
in the entered design. If the device fitting process includes
errors, a window will again describe them. A detailed report file
is generated indicating the resources required to fit the input
design and any problems that occurred in the process.
Timing Simulation
The Aldec Active-HDL Sim post-fitting timing simulator pro-
vides timing simulation for PLDs/CPLDs and features interac-
tive waveform viewing as well as graphical creation and editing
of all waveforms. The simulator also provides the ability to
probe internal nodes, and automatically generate clocks and
pulses. The version in Warp Enterprise has the ability to com-
pare waveforms and highlight differences before and after a
design change. In Warp Enterprise there is no maximum sim-
ulation time. To use the timing simulator in Warp Enterprise
Verilog you must use a Verilog netlist.
Warp Enterprise Verilog can also output standard VHDL or
Verilog timing models that all third-party simulators can use to
perform functional and timing verifications of a synthesized
design.
Architecture Explorer
The Architecture Explorer graphically displays how the design
will be implemented on the chip. It provides a view of the entire
device to show what memory elements and logic clusters have
been used for what part of the design. This gives the designer
an idea of what resources are free. The Architecture Explorer
allows you to zoom in multiple times. At maximum zoom it
displays the logic gate implementation in each macrocell. The
Architecture Explorer is available for PSI, Delta39K, and
Quantum38K devices.
CY3138
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