CY3138R62 Cypress Semiconductor Corp., CY3138R62 Datasheet - Page 2

• Manufacturer Part Number: CY3138R62
• Description: Warp Enterprise Verilog PC
• Manufacturer: Cypress Semiconductor Corp.

can be done very early in the design to verify correct function-
ality, which significantly speeds the design process.
The Warp® syntax for Verilog includes support for intermedi-
ate level entry modes such as state tables and Boolean entry.
At the lowest level, designs can be described using gate-level
descriptions. Warp Enterprise gives the designer the flexibility
to intermix all of these entry modes.
In addition, Verilog allows you to design hierarchically, building
up entities in terms of other entities. This feature allows you to
work either “top-down” (designing the highest levels of the sys-
tem and its interfaces first, then progressing to greater and
greater detail) or “bottom-up” (designing elementary building
blocks of the system, then combining these to build larger and
larger parts) with equal ease.
Because this languages is an IEEE standard, multiple vendors
offer tools for design entry and simulation at both high and low
levels and synthesis of designs to different silicon targets. The
use of device-independent behavioral design entry gives
users the freedom to easily migrate to high volume technolo-
gies. The wide availability of Verilog tools provides complete
vendor independence as well. Designers can begin their
project using Warp Enterprise for Cypress CPLDs and con-
vert to high volume ASICs using the same Verilog behavioral
description with industry-standard synthesis tools.
The Verilog language also allows users to define their own
functions. User-defined functions allow users to extend the
capabilities of the language and build reusable files of tested
routines. Verilog provides control over the timing of events or
processes. It has constructs that identify processes as either
sequential, concurrent, or a combination of both. This feature
is essential when describing the interaction of complex state
machines.
Document #: 38-03045 Rev. *A
Verilog
text
Programming
File
Figure 1. Warp
Source-Level
Simulation
Graphical
HDL Blocks
®
UltraGen
Synthesis
Simulator
Design Flow
Timing
Fitting
and
™
State Machine
Simulation Models
VHDL, Verilog
&Third-Party
Verilog is a rich programming language. Its flexibility reflects
the nature of modern digital systems and allows designers to
create accurate models of digital designs. Because it is not a
verbose language it is easy to learn and compile. In addition,
models created in Verilog can readily be transported to other
EDA Environments. Warp Enterprise Verilog supports IEEE
1364 Verilog including loops, reduction and conditional op-
erators.
A Verilog Design Example
Design Entry
Warp Enterprise descriptions specify:
The part of a Warp Enterprise description that specifies the
behavior or structure of the design is called a module. The
module declares the design’s interface signals (i.e., defines
what external signals the design has, and what their direc-
tions and types are).
The module portion of a design file is a declaration of what a
design presents to the outside world (the interface). For each
external signal, the module specifies a signal name, a direction
and a data type. In addition, the module declaration specifies
a name by which the entity can be referenced in other
modules. This section shows code segments from four sample
design files. The top portion of each example features the
module declaration.
Behavioral Description
The module portion of a design file specifies the function of the
design. As shown in Figure 1, multiple design-entry methods
are supported in Warp Enterprise. A behavioral description
in Verilog often includes well known constructs such as
If Else, and Case statements. Here is a code segment
from a simple state machine design (soda vending ma-
chine) that uses behavioral Verilog to implement the de-
sign:
MODULE drink (nickel, dime, quarter, clock,
REG[1:0] drinkStatus;
ALWAYS@ (POSEDGE clock)
BEGIN
• The behavior or structure of a design, and
• the mapping of signals in a design to the pins of a PLD/CPLD
INPUT nickel, dime, quarter, clock;
OUTPUT returnDime,returnNickel,giveDrink;
REG returnDime, returnNickel, giveDrink;
PARAMETER zero = 0, five = 1, ten = 2,
fifteen = 3, twenty = 4, twentyfive = 5
owedime = 6;
giveDrink = 0;
returnDime = 0;
returnNickel = 0;
CASE(drinkStatus)
(optional)
zero: BEGIN
IF (nickel)
returnDime, returnNickel,
giveDrink);
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