CY3138R62 Cypress Semiconductor Corp., CY3138R62 Datasheet - Page 3

• Manufacturer Part Number: CY3138R62
• Description: Warp Enterprise Verilog PC
• Manufacturer: Cypress Semiconductor Corp.

Verilog is not a strongly typed language. The simplicity and
readability of the following code is increased by use of the
CASEX. The CASEX command accepts “Don’t Cares” and
chooses the branch depending on the value of the expression.
MODULE sequence (clk, s);
ALWAYS@(POSEDGE clk)
4’b00XX: BEGIN
4’b01XX: BEGIN
4’b100X: BEGIN
Document #: 38-03045 Rev. *A
ENDCASE
END
ENDMODULE
INPUT clk;
INOUT s;
WIRE s;
REG temp;
REG[3:0] count;
CASEX(count)
END
five: BEGIN
END
// Several states are omitted in this
// example. The omitted states are ten
// fifteen, twenty, and twentyfive.
owedime: BEGIN
END
default: BEGIN
// This makes sure that the state
// machine resets itself if
// it somehow gets into an undefined state.
END
ELSE IF (dime)
ELSE IF (quarter)
IF (nickel)
ELSE IF (dime)
ELSE IF (quarter)
returnDime = 1;
drinkStatus = zero;
drinkStatus = zero;
drinkStatus = five;
drinkStatus = ten;
drinkStatus = twentyfive;
drinkStatus = ten;
drinkStatus = fifteen;
BEGIN
END
drinkStatus = zero;
giveDrink = 1;
temp=1;
count=count+1;
end
temp=0;
count=count+1;
end
default: BEGIN
ENDCASE
ASSIGN s=temp;
ENDMODULE
Boolean Equations
A second design-entry method available to Warp Enterprise
users is Boolean equations. Figure 2 displays a schematic of a sim-
ple one-bit half adder. The following code describes how this one-bit
half adder can be implemented in Warp Enterprise with Boolean
equations:
MODULE half_adder(x, y, sum, carry);
ASSIGN sum = x^y;
ASSIGN carry = x&y;
ENDMODULE
Structural Verilog
While all of the design methodologies described thus far are
high-level entry methods, structural Verilog provides a method
for designing at a very low level. In structural descriptions, the
designer simply lists the components that make up the design
and specifies how the components are wired together.
Figure 3 displays the schematic of a simple 3-bit shift register and
the following code shows how this design can be described in
Warp Enterprise using structural Verilog.
MODULE shifter3 (clk, x, q0, q1, q2);
ENDMODULE;
INPUT x, y;
OUTPUT sum, carry;
INPUT clk, x;
OUTPUT q0, q1, q2;
WIRE q0, q1, q2;
REG q0_temp, q1_temp, q2_temp;
DFF d1(x,clk,q0_temp);
DFF d2(q0_temp,clk,q1_temp);
DFF d3(q1_temp,clk,q2_temp);
ASSIGN q0 = q0_temp;
ASSIGN q1 = q1_temp;
ASSIGN q2 = q2_temp;
y
x
Figure 2. One-Bit Half Adder
temp=1;
count=count+1;
end
temp=0;
count=0;
end
Sum
Carry
CY3138
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