AD9857 Analog Devices, AD9857 Datasheet - Page 27

• Manufacturer Part Number: AD9857
• Description: CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
• Manufacturer: Analog Devices

CIC Overflow Pin
Any condition that leads to an overflow of the CIC filters will cause
signal activity on the CIC_OVRFL pin. The CIC_OVRFL pin
will remain low (Logic 0) unless an overflow condition occurs.
When an overflow condition occurs, the CIC_OVRFL pin does
not remain high, but will toggle in accordance with data going
through the CIC filter.
Clearing the CIC Filter
The AD9857 CIC filter(s) can become corrupted if certain illegal
(i.e., non-valid) operating conditions occur. If the CIC filter(s)
become corrupted, invalid results will be apparent at the output
and the CIC_OVRFL output pin will exhibit activity (toggling
between Logic 0 and Logic 1 in accordance with the data going
through the CIC filter). Examples of situations that may cause
the CIC filter to produce invalid results include:
1. Transmitting data when the PLL is not locked to the reference
2. Operating the part above the maximum specified system clock
3. Changing the CIC filter interpolation rate during transmission.
If the CIC filters become corrupted, the user can take advantage
of the CIC Clear bit (Control Register 00h<7>) to easily clear
the filter(s). By writing the CIC Clear bit to a Logic 1, the AD9857
enters a routine that clears the entire datapath, including the CIC
filter(s). The routine simply ignores the D<13:0> pins and forces
logical zeros on to the I and Q signal processing paths while hold-
ing the CIC filter memory elements reset. The routine is complete
once all data path memory elements are cleared. The CIC clear
bit is also reset, so that the user does not have to explicitly clear it.
NOTE: The time required to complete this routine is a function
of clock speed and the overall interpolation rate programmed
into the device. Higher interpolation rates create lower clock
frequencies at the filters preceding the CIC filter(s), causing the
routine time to increase.
In addition to the capability to detect and clear a corrupted CIC
filter condition, there are several conditions within the AD9857
that cause an automatic datapath flush, which includes clearing
the CIC filter. The following conditions automatically clear the
signal processing chain of the AD9857:
1. Power-On Reset—Proper initialization of the AD9857 requires
2. PLL Not Locked To the Reference Clock—If the PLL Lock
3. Digital Power-Down—When the DPD pin is driven high, the
4. Full Sleep Mode—If the sleep mode control bit is set high,
frequency.
rate (200 MHz).
the Master Reset pin to be active high for at least 5 REFCLK
clock cycles. After Master Reset becomes inactive, the AD9857
completes the datapath clear routine as described above.
Control bit is cleared and the AD9857 detects that the PLL
is not locked to the reference clock input, the AD9857 invokes
and completes the datapath clear routine after lock has been
detected. When the PLL Lock Control bit is set, the datapath
clear routine will not be invoked if the PLL is not locked.
The PLL Lock Control bit is set upon initialization, dis-
abling the clear routine functionality due to the PLL.
AD9857 will automatically invoke and complete the datapath
clear routine before powering down the digital section.
the AD9857 will automatically invoke and complete the
datapath clear routine before powering down.
Digital Power-Down
The AD9857 includes a digital power-down feature that can be
hardware- or software-controlled. Digital power-down allows the
users to save considerable operating power (60–70% reduction)
when not transmitting and requires no “startup” time before the
next transmission can occur. The digital power-down feature is
ideal for burst mode applications where fast “begin to transmit”
time is required.
During digital-power down the internal clock synchronization is
maintained and the PDCLK output continues to run. Reduction
in power is achieved by stopping many of the internal clocks
that drive the signal processing chain.
Invoking the Digital Power-Down causes supply current transients.
Therefore, some users may not want to invoke the DPD function
in order to ease power supply regulation considerations.
Hardware-Controlled Digital Power-Down
The hardware-controlled method for reducing power is to apply
a Logic 1 to the DPD pin. Restarting the part after a Digital
Power-Down is accomplished by applying a logic zero to the DPD
pin. The DPD pin going to Logic 0 can occur simultaneously with
the activation of TxENABLE.
The user will notice some time delay between invoking the digital
power-down function and the actual reduction in power. This is
due to an automatic routine that clears the signal processing chain
before stopping the clocks. Clearing the signal processing chain
before powering down ensures that the AD9857 is ready to transmit
when Digital Power-Down mode is deactivated (see the Clearing
the CIC Filter section for details).
Software-Controlled Digital Power-Down
The software-controlled method for reducing digital power be-
tween transmissions is simply an enable or disable of an automatic
power-down function. When enabled, digital power-down between
bursts occurs automatically after all data has passed the AD9857
signal processing path.
When the AD9857 senses the TxENABLE input indicates the
end of a transmission, an on-chip timer is used to verify that the
data has completed transmission before stopping the internal
clocks that drive the signal processing chain memory elements.
As with the hardware activation method, clock synchronization
is maintained and the PDCLK output continues to run. An active
high signal on TxENABLE automatically restarts the internal
clocks, allowing the next burst transmission to start immediately.
The automatic digital power-down between bursts is enabled by
writing the Control Register 01h<2> bit high. Writing the Con-
trol Register 01h<2> bit low will disable the function.
Full Sleep Mode
When coming out of Full Sleep Mode, it is necessary to wait for
the PLL Lock Indicator to go high. Full Sleep Mode functional-
ity is provided by programming one of the Control Registers
(01h<3>). When the Full Sleep bit is set to a Logic 1, the device
shuts down both its digital and analog sections. During Full Sleep
Mode, the contents of the registers of the AD9857 are main-
tained. This mode yields the minimum possible device power
dissipation.
AD9857