AD9857 Analog Devices, AD9857 Datasheet - Page 10

• Manufacturer Part Number: AD9857
• Description: CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
• Manufacturer: Analog Devices

AD9857
MODES OF OPERATION
The AD9857 has three operating modes:
• Quadrature Modulation Mode (Default)
• Single-Tone Mode
• Interpolating DAC Mode
Mode selection is accomplished by programming a control reg-
ister via the Serial Port. The Inverse SINC filter and output scale
multiplier are available in all three modes.
Quadrature Modulation Mode
In Quadrature Modulation Mode both the I and Q data paths
are active. A block diagram of the AD9857 operating in the
Quadrature Modulation Mode is shown in Figure 16.
In Quadrature Modulation Mode, the PDCLK/FUD pin is an
output and functions as the Parallel Data Clock (PDCLK), which
serves to synchronize the input of data to the AD9857. In this
PARALLEL
DATA IN
(14-BIT)
PDCLK/
FUD
D
M
U
E
X
14
14
TxENABLE
Q
I
CIC FILTER
INVERSE
INV
CIC
RESET
M
U
X
OVERFLOW
CIC
POLATOR
INTER-
FIXED
(4 )
CONTROL REGISTERS
SERIAL
PORT
PROGRAMMABLE
INTERPOLATOR
(2
CIC
– 63 )
POWER-
DIGITAL
POWER-
DOWN
DOWN
LOGIC
TIMING & CONTROL
M
U
X
PROFILE
PS1
SELECT
TUNING
LOGIC
WORD
mode, the input data must be synchronized with the rising edge
of PDCLK. The PDCLK operates at twice the rate of either the
I or Q data path. This is because of the fact that the I and Q data
must be presented to the parallel port as two 14-bit words mul-
tiplexed in time. One I word and one Q word together comprise
one internal sample. Each sample is propagated along the inter-
nal data pathway in parallel fashion.
The DDS Core provides a quadrature (sin and cos) local oscilla-
tor signal to the quadrature modulator, where the I and Q data
are multiplied by the respective phase of the carrier and summed
together, to produce a quadrature-modulated data stream.
All of this occurs in the digital domain, and only then is the digital
data stream applied to the 14-bit DAC to become the quadrature-
modulated analog output signal.
QUADRATURE
MODULATOR
PS0
CORE
DDS
32
M
U
X
SINC FILTER
INVERSE
M
U
X
SINC
INV
MULTIPLIER
(4
CLOCK
M
U
X
LOCK
– 20 )
PLL
14
OUTPUT
SCALE
VALUE
8
AD9857
CONTROL
CLOCK
INPUT
MODE
MODE
14-BIT
DAC
DAC_RSET
IOUT
IOUT
REFCLK
REFCLK