AD9857 Analog Devices, AD9857 Datasheet - Page 26

• Manufacturer Part Number: AD9857
• Description: CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
• Manufacturer: Analog Devices

AD9857
EASE OF USE FEATURES
Profile Select
The profile select pins, PS0 and PS1, activate one of four inter-
nal profiles within the device. A profile is defined as a group of
control registers. The AD9857 contains four identical register
groupings associated with Profile 0, 1, 2, and 3. They are avail-
able to the user to provide rapid changing of device parameters
via external hardware. Profiles are activated by simply control-
ling the logic levels on device pins P0 and P1 as defined in the
table below.
Each profile offers the following functionality:
1. Control of the DDS output frequency via the frequency
2. Control over the sum or difference of the quadrature modu-
3. Ability to bypass the Inverse CIC filter
4. Control of the CIC interpolation rate (1 to 63 ), or bypass
5. Control of the output scale factor (which offers a gain range
The Profile Select Pins are sampled synchronously with the
PDCLK signal for the Quadrature Modulation Mode and the
Interpolating DAC Mode. For Single-Tone Mode they are sampled
synchronously with SYSCLK (internal only).
Setting the Phase of the DDS
A feature unique to the AD9857 (versus previous ADI DDS
products) is the ability for the user to preset the DDS accumu-
lator to a value of 0. This sets the DDS outputs to sin = 0 and
cos = 1. To accomplish this, the user simply programs a tuning
word of 00000000h, which forces the DDS core to a “zero-
phase” condition.
Reference Clock Multiplier
For DDS applications, the carrier is typically limited to about
40% of SYSCLK. For a 65 MHz carrier, the system clock required
is above 160 MHz. To avoid the cost associated with high fre-
quency references, and the noise coupling issues associated with
operating a high-frequency clock on a PC board, the AD9857
provides an on-chip programmable clock multiplier that multiplies
the Reference Clock frequency supplied to the part. The available
clock multiplier range is from 4 to 20 , in integer steps. With the
Reference Clock Multiplier enabled, the input reference clock
required for the AD9857 can be kept in the 10 MHz to 50 MHz
range for 200 MHz system operation, which results in cost and
system implementation savings. The Reference Clock Multiplier
function maintains clock integrity as evidenced by the system
phase noise characteristics of the AD9857. External loop filter
components consisting of a series resistor (1.3 k ) and capaci-
tor (0.01 F) provide the compensation zero for the REFCLK
tuning word
lator components via the Spectral Invert bit (only valid when
the device is operating the Quadrature Modulation Mode)
CIC Interpolator
between 0 and 1.9921875)
PS1
0
0
1
1
Table VI. Profile Select Matrix
PS0
0
1
0
1
Profile
0
1
2
3
Multiplier PLL loop. The overall loop performance has been
optimized for these component values.
Control of the PLL is accomplished by programming the 5-bit
REFCLK Multiplier portion of Control Register 00h.
The PLL may be bypassed by programming a value of 01h.
When bypassed, the PLL is shut down to conserve power.
When programmed for values ranging from 04h–14h (4–20
decimal), the PLL multiplies the REFCLK input frequency by
the corresponding decimal value. The maximum output frequency
of the PLL is restricted to 200 MHz. Whenever the PLL value is
changed, the user should be aware that time must be allocated to
allow the PLL to lock (approximately 1 ms). Indication of the
PLL’s lock status is provided externally via the PLL Lock
Indicator pin.
PLL Lock (See Reference Clock Multiplier)
The PLL Lock indicator (PLL_LOCK) is an active high output
pin, serving as a flag to the user that the device has locked to the
REFCLK signal.
The status of the PLL Lock Indicator can be used to control
some housekeeping functions within the device if the user sets
the PLL Lock Control bit to 0 (Control Register 00h<5>). Assum-
ing that the PLL Lock Control bit is cleared (Logic 0), the status of
the PLL Lock Indicator pin has control over certain internal device
functions. Specifically, if the PLL Lock Indicator is a Logic 0
(PLL not locked), then the following static conditions apply:
1. The accumulator in the DDS core is cleared.
2. The internal I and Q data paths are forced to a value of
3. The CIC filters are cleared.
4. The PDCLK is forced to a Logic 0.
5. Activity on the TxENABLE pin is ignored.
On the rising edge of the PLL Lock Indicator the static condi-
tions mentioned above are removed and the device assumes
normal operation.
If the user requires the PDCLK to continue running, the PLL
Lock Control bit (Control Register 00h<5>) can be set to a
Logic 1. When the PLL Lock Control bit is set, the PLL lock
indicator pin functionality remains the same, but the internal
operations noted in 1 through 5 above will not occur. The
default state of the PLL Lock Control bit is set, suppressing
internal monitoring of the PLL lock condition.
Single or Differential Clock
In a noisy environment, a differential clock is usually considered
superior in performance over a single-ended clock in terms of
jitter performance, noise ingress, EMI, etc. However, sometimes
it is desirable (economy, layout, etc.) to use a single-ended clock.
The AD9857 allows the use of either a differential or single-ended
Reference Clock input signal. A logic high on the DIFFCLKEN
pin selects a differential clock input, whereas a logic low on this
pin selects a single-ended clock input. If a differential clock is to
be used, logic high is asserted on the DIFFCLKEN pin. The
Reference Clock signal is applied to the REFCLK pin, and the
inverted (complementary) Reference Clock signal is applied to
REFCLK. If a single-ended Reference Clock is desired, logic
low should be asserted on the DIFFCLKEN pin, and the Refer-
ence Clock signal applied to REFCLK only. REFCLK is ignored
in single-ended mode, and can be left floating or tied low.
ZERO.