AD9857 Analog Devices, AD9857 Datasheet - Page 12

• Manufacturer Part Number: AD9857
• Description: CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
• Manufacturer: Analog Devices

AD9857
Interpolating DAC Mode
A block diagram of the AD9857 operating in the Interpolating
DAC Mode is shown in Figure 18. In this mode the DDS and
modulator are both disabled and only the I data path is active.
The Q data path is disabled from the 14-bit Parallel Data Port
up to and including the modulator.
As with the Quadrature Modulation Mode, the PDCLK pin is
an output and functions as a clock which serves to synchronize
the input of data to the AD9857. Unlike the Quadrature Modu-
lation Mode, however, the PDCLK operates at the rate of the I
data path. This is because only I data is being presented to the
parallel port as opposed to the interleaved I/Q format of the
Quadrature Modulation Mode.
In the Interpolating DAC Mode, the baseband data supplied at the
parallel port remains at baseband at the output; i.e., no modulation
takes place. However, a sample rate conversion takes place based
on the programmed interpolation rate. The interpolation hardware
performs the necessary signal processing required to eliminate the
aliased images at baseband that would otherwise result from a
sample rate conversion. The interpolating DAC function is effec-
tively an oversampling operation with the original input spectrum
intact but sampled at a higher rate.
Signal Processing Path
To better understand the operation of the AD9857 it is helpful to
follow the signal path from input, through the device, to the
output, examining the function of each block (refer to the Func-
tional Block Diagram). The input to the AD9857 is a 14-bit
parallel data path. This assumes that the user is supplying the
data as interleaved I and Q values. Any encoding, interpolation,
and pulse shaping of the data stream should occur before the data is
presented to the AD9857 for upsampling.
PARALLEL
DATA IN
(14-BIT)
PDCLK/
FUD
M
D
E
U
X
14
TxENABLE
I
CIC FILTER
INVERSE
INV
CIC
RESET
M
U
X
OVERFLOW
CIC
POLATOR
INTER-
FIXED
CONTROL REGISTERS
(4 )
SERIAL
PORT
PROGRAMMABLE
INTERPOLATOR
(2
CIC
– 63 )
POWER-
POWER-
DIGITAL
DOWN
DOWN
LOGIC
TIMING & CONTROL
M
U
X
PROFILE
PS1
SELECT
LOGIC
The AD9857 demultiplexes the interleaved I and Q data into two
separate data paths inside the part. This means that the input
sample rate (f
the AD9857, must be 2 the internal I/Q Sample Rate (f
the rate at which the I/Q pairs are processed. In other words,
f
From the input demultiplexer to the Quadrature Modulator, the
data path of the AD9857 is a dual I/Q path.
All timing within the AD9857 is provided by the internal System
Clock (SYSCLK) signal. The externally provided Reference
Clock signal may be used as is (1 ), or multiplied by the internal
Clock Multiplier (4 –20 ) to generate the SYSCLK. All other
internal clocks and timing are derived from the SYSCLK.
Input Data Assembler
In the Quadrature Modulation or Interpolating DAC Modes the
device accepts 14-bit, two’s complement data at its parallel data
port. The timing of the data supplied to the parallel port may
be easily facilitated with the PDCLK/FUD pin of the AD9857,
which is an output in the Quadrature Modulation Mode and the
Interpolating DAC mode. In the Single-Tone Mode, the same
pin becomes an input to the device and serves as a FREQUENCY
UPDATE (FUD) strobe.
Frequency control words are programmed into the AD9857 via
the serial port (see the Control Register Description). Since the
serial port is an asynchronous interface, when programming new
frequency tuning words into the on-chip profile registers, the
AD9857’s internal frequency synthesizer must be synchronized
with external events. The purpose of the FUD input pin is to
synchronize the start of the frequency synthesizer to the external
timing requirements of the user. The rising edge of the FUD
signal causes the frequency tuning word of the selected profile
DATA
PS0
= 2
f
IQ
DATA
.
SINC FILTER
), the rate at which 14-bit words are presented to
INVERSE
M
U
X
SINC
INV
MULTIPLIER
(4
CLOCK
M
U
X
LOCK
– 20 )
PLL
14
OUTPUT
SCALE
VALUE
8
AD9857
CONTROL
CLOCK
INPUT
MODE
MODE
14-BIT
DAC
DAC_RSET
IOUT
IOUT
REFCLK
REFCLK
IQ
),