AD9854 Analog Devices, AD9854 Datasheet - Page 9

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

Figures 8–11 show the trade-off in elevated noise floor, increased phase noise, and occasional discrete spurious energy when the
internal REFCLK Multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown.
Figures 12 and 13 show the slight increase in noise floor both with and without the PLL when slower clock speeds are used to generate
the same fundamental frequency, that is, with a 100 MHz clock as opposed to a 300 MHz clock in Figures 10 and 12.
REV. 0
Figure 12. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
100 MHz EXTCLK with REFCLK Multiplier Bypassed
Figure 8. Narrowband SFDR, 39.1 MHz, 1 MHz BW,
300 MHz EXTCLK with REFCLK Multiply Bypassed
Figure 9. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
300 MHz EXTCLK with REFCLK Multiplier Bypassed
–100
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
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–80
–90
0
0
0
CENTER 39.1MHz
CENTER 39.1MHz
CENTER 39.1MHz
100kHz/
5kHz/
5kHz/
SPAN 50kHz
SPAN 50kHz
SPAN 1MHz
–9–
Figure 11. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
30 MHz EXTCLK/REFCLK Multiplier = 10
Figure 13. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
10 MHz EXTCLK with REFCLK Multiplier = 10
Figure 10. Narrowband SFDR, 39.1 MHz, 1 MHz BW,
30 MHz EXTCLK with REFCLK Multiply = 10
–100
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
CENTER 39.1MHz
CENTER 39.1MHz
CENTER 39.1MHz
100kHz/
5kHz/
5kHz/
AD9854
SPAN 50kHz
SPAN 50kHz
SPAN 1MHz