AD9854 Analog Devices, AD9854 Datasheet - Page 16

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

Multiplier Value
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AD9854
Inverse SINC Function
This filter precompensates input data to both DACs for the
SIN(x)/x roll-off function to allow wide bandwidth signals (such
as QPSK) to be output from the DACs without appreciable
amplitude variations that will cause increased EVM (error vector
magnitude). The inverse SINC function may be bypassed to
significantly reduce power consumption, especially at higher
clock speeds. When the Q DAC is configured as a “control”
DAC, the inverse SINC function does not apply.
Inverse SINC is engaged by default and is bypassed by bringing
the “Bypass Inv SINC” bit high in control register 20 (hex) in
Table V.
REFCLK Multiplier
This is a programmable PLL-based reference clock multiplier
that allows the user to select an integer clock multiplying value
over the range of 4 to 20 by which the REFCLK input will be
multiplied. Use of this function allows users to input as little as
15 MHz to produce a 300 MHz internal system clock. Five bits
in control register 1E hex set the multiplier value as follows in
Table I.
Figure 33. Normal SIN(x)/x DAC Output Power Envelope
Filter
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
CENTER 50MHz
FUNDAMENTAL OUTPUT POWER DECREASES
WITH INCREASING FREQUENCY
IMAGES
Ref Mult 4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
10MHz/
Table I. REFCLK Multiplier Control Register Values
SPAN 100MHz
Ref Mult 3
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
–16–
The REFCLK Multiplier function can be bypassed to allow
direct clocking of the AD9854 from an external clock source.
The system clock for the AD9854 is either the output of the
REFCLK Multiplier (if it is engaged) or the REFCLK inputs.
REFCLK may be either a single-ended or differential input by
setting Pin 64, DIFF CLK ENABLE, low or high respectively.
PLL Range Bit
The PLL Range Bit selects the frequency range of the REFCLK
Multiplier PLL. For operation from 200 MHz to 300 MHz
(internal system clock rate) the PLL Range Bit should be set to
Logic 1. For operation below 200 MHz, the PLL Range Bit
should be set to Logic 0. The PLL Range Bit adjusts the PLL
loop parameters for optimized phase noise performance within
each range.
Pin 61, PLL FILTER
This pin provides the connection for the external zero compen-
sation network of the PLL loop filter. The zero compensation
network consists of a 1.3 k resistor in series with a 0.01 F
capacitor. The other side of the network should be connected to
as close as possible to Pin 60, AVDD. For optimum phase noise
performance the clock multiplier can be bypassed by setting the
“Bypass PLL” bit in control register address 1E.
Figure 34. Inverse SIN(x)/x (Inverse SINC) Filter Engaged
Ref Mult 2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
CENTER 50MHz
FUNDAMENTAL OUTPUT POWER IS
"FLAT" FROM DC TO 1/2 FCLK
Ref Mult 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
10MHz/
SPAN 100MHz
Ref Mult 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
REV. 0