AD9854 Analog Devices, AD9854 Datasheet - Page 27

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

Interfacing and Programming the AD9854
The AD9854 Register Layout, shown in Table V, contains the
information that programs the chip for the desired functionality.
While many applications will require very little programming to
configure the AD9854, some will make use of all twelve acces-
sible register banks. The AD9854 supports an 8-bit byte parallel
I/O operation or an SPI-compatible serial I/O operation. All
accessible registers can be written and read back in either
I/O operating mode.
An external pin, S/P SELECT, is used to configure the I/O mode.
Systems that use the parallel I/O mode must connect the S/P
SELECT pin to V
must tie the S/P SELECT pin to GND.
Regardless of mode, the I/O port data is written to a buffer
memory that does NOT affect operation of the part until the
contents of the buffer memory are transferred to the register
banks. This transfer of information occurs synchronously to the
system clock and occurs in one of two ways:
REV. 0
A<5:0>
D<7:0>
A<5:0>
D<7:0>
WR
RD
DD
. Systems that operate in the serial I/O mode
A1
A1
D1
T
RDHOZ
SPECIFICATION
D1
T
T
T
T
T
SPECIFICATION
T
AHD
ADV
AHD
RDLOV
RDHOZ
WRHIGH
T
T
T
T
T
T
T
ASU
DSU
ADH
DHD
WRLOW
WRHIGH
WR
Figure 50. Parallel Port Write Timing Diagram
Figure 49. Parallel Port Read Timing Diagram
T
ASU
T
T
RDLOV
ADV
VALUE
15ns
15ns
10ns
5ns
T
WR
VALUE
4ns
2ns
5ns
0ns
3ns
7ns
3ns
T
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
DESCRIPTION
WRLOW
T
DESCRIPTION
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL INACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
WR SIGNAL MINIMUM PERIOD
DSU
A2
A2
D2
–27–
1. Internally, controlled at a rate programmable by the user or,
2. Externally, controlled by the user. I/O operations can occur in
Parallel I/O Operation
With the S/P SELECT pin tied high, the parallel I/O mode is
active. The I/O port is compatible with industry standard DSPs
and microcontrollers. Six address bits, eight bidirectional data
bits and separate write/read control inputs make up the I/O
port pins.
Parallel I/O operation allows write access to each byte of any
register in a single I/O operation at 100 MHz. Read back capability
for each register is included to ease designing with the AD9854.
Reads are not guaranteed at 100 MHz as they are intended for
software debug only.
Parallel I/O operation timing diagrams are shown in the Figures
49 and 50.
D2
the absence of REFCLK but the data cannot be moved from
the buffer memory to the register bank without REFCLK.
See the Update Clock Operation section of this document
for details.
T
AHD
T
DHD
A3
A3
D3
D3
AD9854