AD9854 Analog Devices, AD9854 Datasheet - Page 19

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

Ramped FSK (Mode = 010)
A method of FSK whereby changes from F1 to F2 are not
instantaneous but, instead, are accomplished in a frequency
sweep or “ramped” fashion. The “ramped” notation implies
that the sweep is linear. While linear sweeping or frequency
ramping is easily and automatically accomplished, it is only one
of many possibilities. Other frequency transition schemes may
be implemented by changing the ramp rate and ramp step size
“on-the-fly,” in piecewise fashion.
Frequency ramping, whether linear or nonlinear, necessitates
that many intermediate frequencies between F1 and F2 will be
output in addition to the primary F1 and F2 frequencies. Figures
37 and 38 graphically depict the frequency versus time charac-
teristics of a linear ramped FSK signal.
The purpose of ramped FSK is to provide better bandwidth
containment than traditional FSK by replacing the instantaneous
frequency changes with more gradual, user-defined frequency
changes. The dwell time at F1 and F2 can be equal to or much
greater than the time spent at each intermediate frequency. The
user controls the dwell time at F1 and F2, the number of inter-
mediate frequencies and time spent at each frequency. Unlike
unramped FSK, ramped FSK requires the lowest frequency to be
loaded into F1 registers and the highest frequency into F2 registers.
Several registers must be programmed to instruct the DDS
regarding the resolution of intermediate frequency steps (48
bits) and the time spent at each step (20 bits). Furthermore, the
CLR ACC1 bit in the control register should be toggled (low-high-
low) prior to operation to assure that the frequency accumulator
is starting from an “all zeros” output condition. For piecewise,
nonlinear frequency transitions, it is necessary to reprogram the
registers while the frequency transition is in progress to affect the
desired response.
Parallel register addresses 1A–1C hex comprise the 20-bit “Ramp
Rate Clock” registers. This is a countdown counter that outputs
a single pulse whenever the count reaches zero. The counter
is activated any time a logic level change occurs on FSK input
Pin 29. This counter is run at the System Clock Rate, 300 MHz
maximum. The time period between each output pulse is given as
REV. 0
(N+1) (SYSTEM CLOCK PERIOD)
FSK DATA
MODE
TW1
TW2
000 (DEFAULT)
F2
F1
0
0
0
Figure 38. Ramped FSK Mode
–19–
010 (RAMPED FSK)
where N is the 20-bit ramp rate clock value programmed by the
user. Allowable range of N is from 1 to (2
this counter clocks the 48-bit Frequency Accumulator shown
below in Figure 39. The Ramp Rate Clock determines the amount
of time spent at each intermediate frequency between F1 and F2.
The counter stops automatically when the destination frequency
is achieved. The “dwell time” spent at F1 and F2 is determined
by the duration that the FSK input, Pin 29, is held high or low
after the destination frequency has been reached.
Parallel register addresses 10–15 hex comprise the 48-bit, straight
binary, “Delta Frequency Word” registers. This 48-bit word
is accumulated (added to the accumulator’s output) every time
it receives a clock pulse from the ramp rate counter. The output
of this accumulator is then added to or subtracted from the F1
or F2 frequency word, which is then fed to the input of the 48-bit
Phase Accumulator that forms the numerical phase steps for the
sine and cosine wave outputs. In this fashion, the output frequency
is ramped up and down in frequency, according to the logic-
state of Pin 29. The rate at which this happens is a function of
the 20-bit ramp rate clock. Once the destination frequency is
achieved, the ramp rate clock is stopped, which halts the frequency
accumulation process.
48-BIT DELTA-
FREQUENCY
F2
Figure 39. Block Diagram of Ramped FSK Function
F1
WORD
ACCUMULATOR
FREQUENCY
RAMP RATE
CLOCK
20-BIT
FREQUENCY
WORD 1
TUNING
(PIN 29)
ADDER
FSK
FREQUENCY
TUNING
WORD 2
ACCUMULATOR
20
–1). The output of
PHASE
SYSTEM
CLOCK
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