USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 5

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

DESCRIPTION OF PIN FUNCTIONS
SMSC DS – USB97C100
NUMBER
104, 106,
105, 107,
QFP PIN
112-115,
108, 110
109, 111
117-120
19-13,
127-7,
9-12
100
103
122
123
124
125
126
READY
DRQ[3:0]
nDACK
[3:0]
TC
SA[19:0]
SD[7:0]
AEN
nIOW
nIOR
nMEMR
nMEMW
SYMBOL
Channel is ready when high.
ISA memory or slave devices use this signal to lengthen a bus
cycle from the default time. Extending the length of the bus
cycle can only be done when the bus cycles are derived from
the Internal DMA controller core. 8051 MCU generated Memory
or I/O accesses cannot and will not be extended even if
READY is asserted low by an external ISA slave device. The
external slave device negates this signal after decoding a valid
address and sampling the command signals (nIOW, nIOR,
nMEMW, and nMEMR). When the slave’s access has
completed, this signal should be allowed to float high.
DMA Request channels 3-0; active high.
These signals are used to request DMA service from the DMA
controller. The requesting device must hold the request signal
until the DMA controller drives the appropriate DMA
acknowledge signal (nDACK[3:0]).
DMA Acknowledge channels 3-0; active low.
These signals are used to indicate to the DMA requesting
device that it has been granted the ISA bus.
DMA Terminal Count; active high.
This signal is used to indicate that a DMA transfer has
completed.
System Address Bus
These signals address memory or I/O devices on the ISA bus.
System Data Bus
These signals are used to transfer data between system
devices.
Address Enable
This signal indicates address validation to I/O devices. When
low this signal indicates that an I/O slave may respond to
addresses and I/O commands on the bus. This signal is high
during DMA cycles to prevent I/O slaves from interpreting DMA
cycles as valid I/O cycles.
I/O Write; active low.
This signal indicates to the addressed ISA I/O slave to latch
data from the ISA bus.
I/O Read; active low.
This signal indicates to the addressed ISA I/O slave to drive
data on the ISA bus.
Memory read; active low
Memory write; active low
This signal indicates to the addressed ISA memory slave to
latch data from the ISA bus.
This signal indicates to the addressed ISA memory slave to
Table 1 - USB97C100 Pin Configuration
ISA INTERFACE
drive data on the ISA bus.
Page 5
PIN DESCRIPTION
BUFFER
TYPE
I/O8
Rev. 01/03/2001
O8
O8
O8
O8
O8
O8
O8
O8
IP
I