USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 43

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

SMSC DS – USB97C100
BIT
BIT
1
0
7
6
5
4
3
2
1
0
(0x7F61 - RESET=0x55)
(0x7F62 - RESET=0x55)
EP11TX_EMPTY
EP10TX_EMPTY
EP4TX_EMPTY
EP9TX_EMPTY
EP8TX_EMPTY
EP11TX_FULL
EP10TX_FULL
EP4TX_FULL
EP9TX_FULL
EP8TX_FULL
TXSTAT_C
STAT_B
NAME
NAME
Table 72 - Transmit FIFO Status Register C
R/W
R/W
R
R
R
R
R
R
R
R
R
R
Endpoint 4 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 11 Transmit Packet FIFO Status
Bits [7:6]='11' Invalid
Bits [7:6]='10' Empty (No Packets queued)
Bits [7:6]='01' Full (5 Packets queued)
Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 10 Transmit Packet FIFO Status
Bits [5:4]='11' Invalid
Bits [5:4]='10' Empty (No Packets queued)
Bits [5:4]='01' Full (5 Packets queued)
Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 9 Transmit Packet FIFO Status
Bits [3:2]='11' Invalid
Bits [3:2]='10' Empty (No Packets queued)
Bits [3:2]='01' Full (5 Packets queued)
Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)
Endpoint 8 Transmit Packet FIFO Status
Bits [1:0]='11' Invalid
Bits [1:0]='10' Empty (No Packets queued)
Bits [1:0]='01' Full (5 Packets queued)
Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)
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TRANSMIT FIFO STATUS REGISTER B
TRANSMIT FIFO STATUS REGISTER C
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001