USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 15

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USB97C100

Manufacturer Part Number
USB97C100
Description
USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
Manufacturer
Standard Microsystems Corporation
Datasheet
MMU Block Register Summary
SMSC DS – USB97C100
ADDRESS
0x6000
7F6E
7F6F
7F50
7F51
7F52
7F53
7F54
7F55
7F56
7F57
7F58
7F59
7F60
7F61
7F62
7F63
7F64
7F65
7F66
7F67
MMUTX_SEL
PAGS_FREE
MMU_TESTx
MMU_TESTx
MMU_TESTx
MMU_TESTx
MMU_TESTx
MMU_DATA
TXSTAT_C
TXSTAT_D
TXSTAT_A
TXSTAT_B
TX_MGMT
TX_MGMT
POP_TX
MMUCR
RXFIFO
NAME
PRH
ARR
PNR
PRL
Table 7 - MMU Block Register Summary
MMU REGISTERS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
N/A
N/A
N/A
W
R
R
R
R
R
R
R
R
Page 15
8051-MMU Data Window Register FIFO
8051-MMU Pointer Register (Low)
8051-MMU Pointer Register (High) & R/W
8051-MMU TX FIFO Select for Commands
8051-MMU Command Register
8051-MMU Allocation Result Register
8051-MMU Packet Number Register
Pages Free In the MMU
TX Management Register 2
RX Packet FIFO Register (All EPs)
POP TX FIFO
TX Packet FIFO Status Register (EP0-3)
TX Packet FIFO Status Register (EP4-7)
TX Packet FIFO Status Register (EP8-11)
TX Packet FIFO Status Register (EP12-15)
Reserved for Test
Reserved for Test
Reserved for Test
TX Management Register 1
Reserved for Test
Reserved for Test
DESCRIPTION
Rev. 01/03/2001

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