USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 18

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

Notes:
SMSC DS – USB97C100
These bits are cleared each time this register is read.
The RX_OVRN interrupt should be considered by firmware as a general Receive Overrun of the SIE, meaning
that a packet destined for the RAM buffer could not be received and was not acknowledged back to the Host.
The firmware should check to see if the RX Packet Number FIFO Register (RXFIFO) is full. If it is empty, then
there may be too many transmit packets queued for the device to receive anything, or the last packet may have
been corrupted on the wire. If it is not empty, then one or more receive packets must be dequeued before the
device can continue to receive packets. In the normal course of operation, the MCU should respond to a
RX_PKT interrupt as often as possible and let the buffering logic do its job.
[7:5]
BIT
4
3
2
1
0
(0x7F02- RESET=0x00)
BIT
7
6
5
4
3
2
1
0
(0x7F01- RESET=0xFF)
PWR_MNG
RX_OVRN
Reserved
ALLOC
NAME
ISR_1
EOT
SOF
TX_EMPTY
IMR_0
RX_PKT
ISADMA
TX_PKT
NAME
IRQ3
IRQ2
IRQ1
IRQ0
R/W
R
R
R
R
R
Table 11 - Interrupt 1 Source Register
Table 10 - Interrupt 0 Mask
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
1 = The SIE returned to Idle State. Marks the end of each
transaction.
1 = When a Start of Frame token is correctly decoded.
Generated by the write strobe to the Frame Count register.
1 = MCU Software Allocation Request complete interrupt. This
interrupt is not generated for hardware (SIEDMA) allocation
requests.
1 = A receive condition has occurred that will stop the current
receive buffer to not be processed The SIE automatically
recovers from this condition after its cause has been
alleviated (e.g. any partially allocated packets will be released.
See Note 2).
1 = A wakeup or power management event in the WU_SRC_1
or WU_SRC_2 registers has gone active.
External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
External interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
Received Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Transmit Queue Empty MMU Interrupt
0 = Enable Interrupt
1 = Mask Interrupt
Transmit Packet MMU Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
ISADMA Status Change Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Page 18
INTERRUPT 1 SOURCE REGISTER
INTERRUPT 0 MASK REGISTER
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001