USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 32

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

Note:
Note:
Note:
Note:
SMSC DS – USB97C100
[7:0]
[7:0]
[7:0]
[7:0]
BIT
BIT
[14:10]
[9:0]
SA[19..15] are driven low when the 8237 is accessing external ISA memory. PTR10 is driven low when the
8237 is accessing internal buffer RAM. Note that the actual transfer size for the ISADMA is limited to 1024
bytes, which limits the payload data to 1016 bytes per transfer when the 8 byte header is skipped. Also note
that the 8051 still has access to 1Meg of external RAM through the MEMBASE register and it is
independent of the 8237's 32k external limit.
Byte F/F is an internal Flip Flop which reflects which byte (high or low) is being written. The CLEAR_FF
register should be written to before writing this register to guarantee which byte (high or low) is being
written. See the Address Programming Table for 16 bit Address definitions.
The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See Address Programming Table for 16 bit Address definitions.
The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or
low) is being written. See the Address Programming Table for 16 bit Address definitions.
BIT
[7:0]
[7:0]
15
BIT
CH0_ADDRH
CH0_ADDRL
CH0_CNTH
CH0_CNTL
(ISA 0x0000)
(ISA 0x0001)
CH0_ADDR
CH1_ADDRH
CH1_ADDRL
CH0_CNT
PN[4:0]/SA[14:10]
NAME
NAME
(ISA 0x0002)
PTR[9:0]/SA[9:0]
CH1_ADDR
NAME
INT_EXT
NAME
8237 INTERNAL ADDRESS PROGRAMMING GUIDE
Table 41 - Channel 0 Current Address Register
Table 43 - Channel 1 Current Address Register
Table 40 - 8237 Address Programming Guide
R/W
R/W
R/W
R/W
R/W
R/W
Table 42 - Channel 0 Byte Count Register
R/W
R/W
R/W
Indicates whether this address refers to Internal Buffer RAM or
External ISA Memory Space
0 = External
1 = Internal
When this bit is set to zero (0), I/O capability is added to External
Memory DMA. This capability can only be used for DMA channels 2
or 3.
External Address -or- Internal Packet Number
SA[14..10] when INT_EXT=0
PN[4..0] when INT_EXT=1
External Address -or- Internal Packet Offset Pointer
SA[9..0] when INT_EXT=0
PTR[9..0] when INT_EXT=1
Lower 8 bits of Base and Current Address when Byte F/F = 0
Upper 8 bits of Base and Current Address when Byte F/F = 1
Lower 8 bits of Byte Count when Byte F/F = 0
Upper 8 bits of Byte Count when Byte F/F = 1
Lower 8 bits of Base and Current Address when Byte F/F = 0
Upper 8 bits of Base and Current Address when Byte F/F = 1
Page 32
CHANNEL 0 CURRENT ADDRESS
CHANNEL 1 CURRENT ADDRESS
CHANNEL 0 BYTE COUNT
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001