L64777 LSI Logic Corporation, L64777 Datasheet - Page 76
L64777
Manufacturer Part Number
L64777
Description
DVB Qam Modulator
Manufacturer
LSI Logic Corporation
Datasheet
1.L64777.pdf
(124 pages)
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4.2.7 Registers 21 and 22
4.2.8 Registers 23 and 24
4.2.9 Register 25
4.2.10 Registers 26, 27, and 28
4-14
15
15
23
7
REF_DUR
PROB_DUR
N_PCLK
NM_COUNT
Register Descriptions
Duration Between NCO Step Updates
This parameter determines the duration between the
NCO step updates in multiples of the sync length. These
are NCO-related register fields; they are used only in PLL
Mode 2. Bit 0 resets to 1; all other bits reset to 0.
Byte Clock Duration
This parameter determines the duration for the byte clock
measurement in units of 256 ICLK cycles. These are
NCO-related register fields; they are used only in PLL
Mode 2. The reset value is 0.
PCLK Cycles
This is the number of PCLK cycles during one ICLK byte
clock. The value in this register is valid only if the
MEASUREMENT_DONE bit in the NCO control register
is set. These are NCO-related register fields; they are
used only in PLL Mode 2. The reset value is 0.
This value is the number of CLK cycles found within the
duration of the (n
NM_COUNT
PROB_DUR
REF_DUR
N_PCLK
1) PCLK cycles. The value in this
R/W [7:0], R
R/W [15:0]
R/W [15:0]
R [23:0]
0
0
0
0
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