STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 60

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

Registers and descriptors description
60/82
Table 10.
LL* = Latching Low and clear by read. LH* = Latching High and clear by read.
XR2(offset = bch) - PID1, PHY identifier 1
XR3(offset = c0h) - PID2, PHY identifier 2
15~10
10~6
15~0
Bit #
9~4
3~0
12
11
5
4
3
2
1
0
PHYID1
PHYID2
MODEL
Transceiver registers description (continued)
Name
10HD
10FD
LINK
ANC
REV
EXT
JAB
RF
AN
---
10BASE-T full duplex ability.
Always 1, since STE10/100A has 10Base-T full
duplex ability.
10BASE-T half duplex ability.
Always 1, since STE10/100A has 10Base-T half
duplex ability.
Reserved
Auto-negotiation completed.
0: Auto-negotiation process incomplete.
1: Auto-negotiation process complete.
Result of remote fault detection.
0: no remote fault condition detected.
1: remote fault condition detected.
Auto-negotiation ability.
Always 1, since STE10/100A has auto-
negotiation ability.
Link status.
0: a link failure condition occurred. Readin clears
this bit.
1: valid link established.
Jabber detection.
1: jabber condition detected (10Base-T only).
Extended register support.
Always 1, since STE10/100A supports extended
register
Part one of PHY identifier.
Assigned to the 3
Organizationally Unique Identifier (The ST OUI
is 0080E1 hex).
Part two of PHY identifier.
Assigned to the 19
organizationally unique identifier (OUI).
Model number of STE10/100A.
6-bit manufacturer’s model number.
Revision number of STE10/100A.
4-bits manufacturer’s revision number.
rd
Description
th
to 18
to 24
th
th
bits of the
bits of the
000000b
000001b
Default
1C04h
0000b
1
1
0
0
1
0
0
1
0
STE10/100A
RW type
RO/LH*
RO/LH*
RO/LL*
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO