STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 50

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

Registers and descriptors description
50/82
Table 8.
Offset value is from 0-255 (8-bit width). To load the whole wake-up frame filtering information, consecutive 25
CSR15 (offset = 78h), WTMR - Watchdog timer
31~6
Bit #
long words write operation to CSR14 should be done.
5
4
3
0024h
0028h
002ch
0030h
0034h
0038h
003ch
0040h
0044h
0048h
004ch
0050h
0054h
0058h
005ch
0060h
Control/status register description (continued)
Name
RWR
RWD
---
---
Reserved
Receive watchdog release. The time (in bit-
times) from sensing dropped carrier to releasing
watchdog timer.
0: 24 bit-times
1: 48 bit-times
Receive watchdog disable
0: If the received packet‘s length exceeds 2560
bytes, the watchdog timer will expire.
1: disable the receive watchdog.
Reserved
CRC16 of pattern 2
CRC16 of pattern 3
CRC16 of pattern 4
CRC16 of pattern 5
Description
Wake-up pattern 3 mask bits 127:96
Wake-up pattern 4 mask bits 127:96
Wake-up pattern 5 mask bits 127:96
Wake-up pattern 3 mask bits 63:32
Wake-up pattern 3 mask bits 95:64
Wake-up pattern 4 mask bits 63:32
Wake-up pattern 4 mask bits 95:64
Wake-up pattern 5 mask bits 63:32
Wake-up pattern 5 mask bits 95:64
Wake-up pattern 3 mask bits 31:0
Wake-up pattern 4 mask bits 31:0
Wake-up pattern 5 mask bits 31:0
Reserved
Reserved
Reserved
Reserved
Default
STE10/100A
pattern 2
pattern 3
pattern 4
pattern 5
RW type
Wake-up
Wake-up
Wake-up
Wake-up
offset
offset
offset
offset