STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 31
STE100A
Manufacturer Part Number
STE100A
Description
PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
Manufacturer
ST Microelectronics, Inc.
Datasheet
1.STE100A.pdf
(82 pages)
- Current page: 31 of 82
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STE10/100A
Table 5.
1. Automatically recalled from EEPROM when PCI reset is deserted
offset
18h~28h
DS(40h), bit15-8, is read/write able register
SIG(80h) is hard wired register, read only
00h
04h
08h
10h
14h
30h
34h
38h
40h
80h
0ch
2ch
3ch
c0h
c4h
STE10/100A configuration registers table
Base class
Max_Lat
Reserved
b31
code
------
Subsystem ID
(1)
Device ID*
-----------
Status
PMC
Min-Gnt
Reserved
Reserved
Subclass
(1)
------
b16
(1)
Signature of STE10/100A
Boot ROM base address
Base memory address
Base I/O address
Latency timer
Driver space
Interrupt pin
Reserved
Reserved
------
Registers and descriptors description
Next_Item_Ptr
b15
Subsystem vendor ID
PMCSR
Vendor ID
Revision #
Command
----------
Cache line size
Interrupt line
(1)
Reserved
Cap_Ptr
Cap_ID
(1)
b0
Step #
31/82
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