CS2412 Amphion, CS2412 Datasheet - Page 5

• Manufacturer Part Number: CS2412
• Description: User-programmable Fft/ifft 1024-point Pipelined
• Manufacturer: Amphion

The kernel operation for 1024-point transform consists of
radix-4 butterfly followed by a twiddle multiplication.
Theoretically in the worst case the result value may grow by a
factor of up to 5.657 in the first stage. This occurs when the
four input data to the radix-4 computation have the maximal
absolute value and the twiddle angle is π/
reaching stage 5 may grow by a factor of up to 1303.793. This
represents a possible wordlength growth of 11 bits. As the
output is 16-bit value and fixed-point arithmetic is employed
in the core, it is necessary to be able to scale the result to avoid
overflow while still obtaining a good dynamic range.
Since the input word length is 16 bits and the output 16 bits,
zero bit growth can be allowed. Thus, the megafunction must
have the capability of up to 11-bit right shifting of the internal
result to enable overflow to be avoided. The total of 11 bit
scaling down operation is assigned to each stage according to
Table 2. When SDC is set to the maximal value, there will be
no overflow for any input data.
The first 4-bits of shift control are mandatory. The remaining
7-bits are applied at the discretion of the user under the
control of SDC.
SDC
000
001
010
011
100
101
110
111
Table 2: Number of Shifting Bits in Each Stage
Stage
1
1
2
2
3
3
3
3
3
SHIFTING CONTROL
Stage
2
1
1
2
2
2
2
2
2
Stage
3
1
1
1
1
2
2
2
2
Stage
4
1
1
1
1
1
1
2
2
4
. The final result
Stage
5
0
0
0
0
0
1
1
2
Total
10
11
4
5
6
7
8
9
A rounding technique is employed to achieve the maximal
computation accuracy possible for the given word lengths.
The core performs the round-to-the-nearest operation to keep
the loss in accuracy minimal. When the intermediate value, for
instance from the twiddle multiplication result, is required to
scale down, the most significant bit of the portion to be
rounded off is added to the word which remains. This is a
compromise
Compared with the technique that unconditionally sets the
bottom bit to '1', the partial rounding scheme achieves better
accuracy and guarantees to generate an all-zero output block
for an all-zero input block.
CS2412 detects overflow at each computation stage and uses
the following procedure to saturate output overflow samples:
If (X >= 32768) X = 32767;
If (X <= -32768) X = -32767;
with respect to SDC signal. Table 3 represents the output error
with respect to SDC signal.
The bit accurate C model provided checks of the output error
COMPUTATION ACCURACY
between
true
rounding
and
truncation.
5
TM