CS2412 Amphion, CS2412 Datasheet - Page 2

• Manufacturer Part Number: CS2412
• Description: User-programmable Fft/ifft 1024-point Pipelined
• Manufacturer: Amphion

FFT (Fast Fourier Transform) and IFFT (Inverse Fast Fourier
Transform) are algorithms computing 2
Fourier transform and inverse discrete Fourier transform, as
defined below
FFT
IFFT:
Where N=2
The
proportional to Nlog
FFT/IFFT is performed. The higher the radix, the less number
of multiplication is required, however the more simultaneous
multiple data access is required which causes the circuits to be
more complicated. The radix-4 algorithm offers a balance
between the computational and circuit complexity and is often
used in construction of higher radix FFT computation units
when designing high performance FFT/IFFT hardware.
2
Y k ( )
CLK
NotRST
TType
SDC
Xre
Xim
XBS
XBIP
YBS
CS2412
Name
=
Y k ( )
computational
N 1
n
FAST FOURIER TRANSFORM
∑
=
–
=
0
p
X n ( )W
--- -
N
and W
1
n
N 1
∑
=
–
I/O
O
O
0
I
I
I
I
I
I
I
–
X n ( )W
N
N
nk
R
= e
N, where R is the radix base on which
, k = 0, 1, 2... N-1
complexity
Width
-j2π/N
1024-Point Pipelined FFT/IFFT
nk
N
16
16
1
1
1
3
1
1
1
, k = 0, 1, 2... N-1
Table 1: CS2412 1024-Point FFT/IFFT Interface Signal Definitions
Data clock signal, rising edge active
Asynchronous global reset signal, active LOW
Static signal specifying the transform type,
0: FFT,
1: IFFT
Input signal specifying the number of bits for the additional scaling down operation, loaded
when XBS is active and associated with the 1024-point block indicated by XBS.
Real component of input data X, in two’s complement format
Imaginary component of input data X, in two’s complement format
Input data X block start signal, active HIGH, associated with the first input data of the N-point
block. The remaining N-1 data of the N-point data block are loaded into the core in the follow-
ing N-1 data clock cycles in the natural order.
Output signal indicating loading X is in Progress. XBIP goes to HIGH the next clock cycle
when XBS is active and returns to LOW when the last data of the N-point block is loaded into
the core. XBS is ignored when it is HIGH.
Output data Y block start signal, active HIGH, asserted when the first data of the N-point
transformed block is on the output port. The remaining N-1 data of the N-point transform
result come out of the core in the following N-1 clock cycles in the natural order.
of
FFT
P
-point discrete
and
IFFT
[1]
[2]
is
Table 1 describes input and output ports (shown graphically
in Figure 2) of the CS2412 1024-point FFT/IFFT core. Unless
otherwise stated, all signals are active high and bit(0) is the
least significant bit.
Figure 2: CS2412 Symbol
NotRST
TType
SDC
XBS
CLK
XRe
Xlm
Description
AND PIN DESCRIPTION
3
16
16
CS2412 SYMBOL
FFT/IFFT
CS2412
1024-pt
16
3
16
XBIP
YBS
YAV
YRe
Ylm
YOV
YSDC