CS2412 Amphion, CS2412 Datasheet - Page 3

• Manufacturer Part Number: CS2412
• Description: User-programmable Fft/ifft 1024-point Pipelined
• Manufacturer: Amphion

The CS2412 performs decimation in frequency (DIF) radix-4
forward or inverse Fast Fourier Transforms on complex data.
Data is loaded into its workspace in normal sequential
(natural) order. The transformed data is returned in normal
sequential order. It performs 1024-point FFT/IFFT using the
following equations:
FFT:
IFFT:
Where N is equal to 1024, SDC is the scaling down control
signal, X(n) is the complex input data and Y(k) the complex
output data. Both the real and imaginary components of input
X(n) and output Y(k) are 16-bit numbers in two's complement
format.
The CS2412 achieves high data throughput rates of up to 50
Msamples/Sec by employing a pipelined architecture with
fixed-point arithmetic operations and pre-scaling strategy to
handle possible overflow in computation. The core has 4-bit
unconditional scaling down operations and 7-bit controlled
scaling down operations specified by input signal SDC, giving
the user the necessary gain control required in a specific
application. The CS2412 core uses radix-4 decimation in
frequency (DIF) algorithm to perform the transform. It
consists of five radix-4 pipelined stages with reshuffle buffers
between stages and is capable of processing continuous data
stream. Both the input and output are in the normal order (the
ordinary time order).
YAV
YRe
YIm
YOV
YSDC
Name
Y k ( )
Y k ( )
=
=
------------------- -
2
------------------- -
2
4
4
I/O
+
O
O
O
O
O
+
1
1
SDC
SDC
n
N 1
N 1
n
∑
=
∑
–
=
Width
–
0
0
X n ( )
16
16
X n ( )
1
1
3
Table 1: CS2412 1024-Point FFT/IFFT Interface Signal Definitions
W
W
–
nk
N
N
nk
Output data Y available indicator, active HIGH, asserted with all data of the N-point transform
result
Real component of output data Y, in two’s complement format, valid only when YAV is HIGH
Imaginary component of output data Y, in two’s complement format, valid only when YAV is
HIGH
Output data Y overflow signal, active HIGH, asserted when overflow occurs during the trans-
form of the output data block.
Output signal indicating the SDC of the output data block
, k = 0, 1, 2 … N-1
, k = 0, 1, 2 … N-1
FUNCTIONAL DESCRIPTION
[3]
[4]
The Selection of transform (FFT/IFFT) is controlled by a static
signal. However, the scaling down control is applied on a
block-by-block basis. The core detects possible overflow
during computation and saturates overflow data accordingly.
In order to minimize the device size, CS2412 uses a 2 x clock
internally. For example, the input data is clocked in using the
data clock while the core operates on the 2 x clock. The output
data is also clocked out on the 2xclock although it changes
only on every 2 cycles of the 2 x clock. When implemented on
FPGA devices, The 2 x clock is generated by the on-chip PLL
of Apex 20KE device or DLL of Virtex devices.
The internal wordlength of each radix-4 operation of CS2412
is specified by Figure 3. The intermediate data stored in the
reshuffle buffers are 16-bit wide (32 bits for complex
numbers). The wordlength grows to 18 bits after the radix-4
butterfly. The twiddle multiplier takes the 18-bit butterfly
output and 16-bit twiddle factors, generating 34-bit product.
The product is then scaled and rounded to 16 bits for the next
stage radix-4 operation.
Figure 3: Wordlength Specification
16 bits
Description
Butterfly
Radix-4
WORD LENGTH
18 bits
16 bits Twiddle factor
Multiply
Twiddle
34 bits
Scaling &
Rounding
Butterfly
Radix-4
16 bits
3
TM