NIS3001 ON Semiconductor, NIS3001 Datasheet
NIS3001
Related parts for NIS3001
NIS3001 Summary of contents
Page 1
... The power density of the NIS3001 is optimized based on MOSFET die size and PInPAK design. The PInPAK layout allows for direct routing into each power terminal. This results in a better thermal solution for the system ...
Page 2
... BST Bootstrap supply voltage input. In conjunction with a Schottky diode to Vs 1.0 mF ceramic capacitor connected between BST and DRN (14). 20 Low Side Driver Output (Bottom Gate, this pin is used to monitor the gate). NIS3001 BST (17) Level Shifter Delay Non−Overlap Control − ...
Page 3
... PGND Ground VIN Input Supply Voltage NOTE: All voltages are with respect to PGND except where noted seconds maximum above 183 C. *The maximum package power dissipation must be observed. NIS3001 Rating Reflow: (SMD styles only) (Note 1) MAX MIN 6.3 V −0 wrt/PGND −0.3 V wrt/DRN 6 ...
Page 4
... Propagation Delay Time, BG Going Low; 50% between CO (going high) and BG (going low) POWER MOSFET ON CHARACTERISTICS High−Side Driver Static Drain−to−Source On−Resistance (VGS = Low−Side Driver Static Drain−to−Source On−Resistance (VGS = NIS3001 = 500 kHz BST EN ...
Page 5
... − P LOSS IN OUT Average VS Voltage Average − Current CO PWM Signal GND This Test Circuit was used to characterize the NIS3001 during operation 5 1.5 V OUT 6 750 kHz Airflow = 200 lfm 5 500 kHz ...
Page 6
... OUTPUT VOLTAGE (V) OUT Figure 10. Efficiency versus Output Voltage Airflow = 200 lfm 80 5.0 Figure 12. Efficiency versus Output Current at NIS3001 2.7 2.6 2.5 2.4 2.3 100 125 4.5 Figure 9. Power Loss versus Driver Voltage 4 500 kHz SW 3.5 3 2.5 OUT = 5 ...
Page 7
... 1. 10.5 mW DS(on) 1.25 1.00 0.75 0.50 −50 − JUNCTION TEMPERATURE ( C) J Figure 13. Top MOSFET On−Resistance Variation with Temperature NIS3001 1. 1. 3.19 mW DS(on) 1.25 1.00 0.75 0.50 100 125 150 −50 − JUNCTION TEMPERATURE ( C) J Figure 14. Bottom MOSFET On−Resistance Variation with Temperature http://onsemi ...
Page 8
... In this mode of operation, the bias current is reduced to a level of 10 mA. When the driver is disabled, the gates of both FETs are low and the drain (DRN) output of the NIS3001 high impedance state. To guarantee system integrity, the driver also incorporates an internal UVLO circuit ...
Page 9
... Signal Ground: The GND pin is the ground pin for the driver, and is internally isolated from the PGND pin. Layout Considerations While the design of the NIS3001 reduces many of the parasitic elements when compared to a discrete solution, careful consideration to layout must still be observed. The ...
Page 10
... NIS3001 CS1N 37 CS2P 38 CS2N 39 CS3P R6* 40 CS3N 41 LIM IP 42 DRP V 43 R5* LIM I 44 IOF R4 REF V 47 CCL V 48 R29 R28 R27 R26 R25 R24 Figure 16. Application Diagram, Three−Phase Converter http://onsemi.com 10 CS5P 24 CS5N 23 CS6P 22 CS6N COMP ...
Page 11
... R21 63. R24,R25,R26,R27,R28, 1.5K R29,R30 24 6 R44,R45,R50,R51,R53, 2.2_ R54, R61 is used to connect the NIS3001 Vs pin to 5V supply only. If different voltage is required items 29 thru 33 are needed. NIS3001 Size Rating Vendor SM C0603 50V muRata Size 10.5mm 4V SANYO OS−CON 3.5mm, 0.60mm SEPC Series SM 1206 6 ...
Page 12
... R8801, R8802 N R501, R502 N R4, R5, R6, R8 N/A R61 is used to connect the NIS3001 Vs pin to 5V supply only. If different voltage is required items 29 thru 33 are needed. NIS3001 Size Rating Vendor SMR0603 “10%, VISHAY 1/10W” LQFP− Semiconductor 6.3 x 6.0 inches FR4 CGI Circuits 10 ...
Page 13
... The QFN platform offers a versatility, which allows either a single or multiple semiconductor devices to be connected together within a leadless package. In this case the NIS3001 Package contains multiple semiconductor devices within one package. This package style was chosen due to its excellent thermal dissipation and reduced electrical parasitics. ...
Page 14
... NIS3001 Footprint Figure 19. Recommended PCB Layout for NIS3001 footprint Thermal/Electrical Vias Vias are normally placed on the larger die attach pads to improve electrical and thermal performance. If vias are required on the larger die attach pads, our recommendation is to use filled−vias. Filled−vias will help prevent the solder ...
Page 15
... Glass” shaped connection is not formed as shown below in Figure 22. “Hour Glass” solder joints are a reliability concern and must be avoided. Preferred Solder Joint Figure 22. Side view of NIS3001 illustrating preferred and undesirable solder joints. http://onsemi.com 15 Peak of 225 C Î ...
Page 16
... Rework Procedure Due to the fact that the NIS3001 is a leadless device, the entire package must be removed from the PC board if there is an issue with the solder joints important to minimize the chance of overheating neighboring devices during the removal of the package since the devices are typically in close proximity with each other ...
Page 17
... 0. 0. DETAIL 0. NOTE NIS3001 PACKAGE DIMENSIONS PInPAK 10.5x10.5 QFN CASE 500−01 ISSUE SEATING A3 C PLANE NOTE NOTE 0. ...
Page 18
... USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 18 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NIS3001/D ...