MX26L12811MC ETC-unknow, MX26L12811MC Datasheet - Page 8

• Manufacturer Part Number: MX26L12811MC
• Description: 128m [x8/x16] Single 3v Page Mode Mtp Memory
• Manufacturer: ETC-unknow

NOTES:
1. Bus operations are defined in Table 1.
2. X = Any valid address within the device.
3. ID = Data read from Identifier Codes.
4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock
6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state.
7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.
9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.
10.Attempts to issue a block erase or program to a locked block.
11.Either 40H or 10H are recognized by the WSM as the byte/word program setup.
12.The clear block lock-bits operation simultaneously clears all block lock-bits.
P/N:PM0990
BA = Address within the block.
IA = Identifier Code Address: see Figure 2 and Table 13.
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register. This data is presented to the device on A15~A0 ; all
other address inputs are ignored.
QD = Data read from Query database.
SRD = Data read from status register. See Table 14 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
CC = Configuration Code.
codes. See Section 4.3 for read identifier code data.
Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =000FH.
The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the
sequence aborts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional
information.
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MX26L12811MC
REV. 1.0, OCT. 29, 2003