MX26L12811MC ETC-unknow, MX26L12811MC Datasheet
MX26L12811MC
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MX26L12811MC Summary of contents
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... GENERAL DESCRIPTION The MXIC's MX26L12811MC series MTP use the most advance 2 bits/cell Nbit technology, double the storage capacity of memory cell. The device provide the high density MTP memory solution with reliable performance and most cost-effective ...
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... Q13 Q12 Q10 VCC Q11 P/N:PM0990 MX26L12811MC PIN DESCRIPTION SYMBOL PIN NAME A0~A22 Address Input Q0~Q15 Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input VCC Device Power Supply GND Device Ground 2 REV. 1.0, OCT. 29, 2003 ...
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... BLOCK DIAGRAM CONTROL CE INPUT OE WE LOGIC ADDRESS LATCH A-1~A22 AND BUFFER Q0-Q15 P/N:PM0990 MX26L12811MC PROGRAM/ERASE HIGH VOLTAGE MTP ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 3 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND DATA DECODER COMMAND DATA LATCH REV ...
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... Block 7E0000 . . . 3FFFFF 128-Kbyte Block 3E0000 . . . 03FFFF 128-Kbyte Block 020000 01FFFF 128-Kbyte Block 000000 Byte Mode (x8) P/N:PM0990 MX26L12811MC A22~A0 7FFFFF 127 64-Kword Block 7F0000 3FFFFF 63 64-Kword Block 3F0000 1FFFFF 31 64-Kword Block 1F0000 01FFFF 1 64-Kword Block 010000 00FFFF 0 64-Kword Block ...
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... See Section , "Read Query Mode Command" for read query data. 6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VCC is within specification. 7. Refer to Table 2 on page 7 for valid DIN during a write operation. P/N:PM0990 MX26L12811MC Standby Read ID Read Read ...
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... OUTPUT DISABLE When VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. P/N:PM0990 MX26L12811MC STANDBY When CE disable the device (see table1) and place it in standby mode. The power consumption of this device is reduced. Data input/output are in a high-impedance(High- Z) state ...
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... Program Notes 10,11 Bus Write Cycles Req'd 2 First Bus Operation(2) Write Write Cycle Address(3) X Data(4,5) 40H/10H Second Bus Operation(2) Write Write Cycle Address(3) PA Data(4,5) PD P/N:PM0990 MX26L12811MC Read Read Read ID Query Status Register 5 6 > 2 > Write Write Write 90H 98H 70H ...
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... The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued. 10.Attempts to issue a block erase or program to a locked block. 11.Either 40H or 10H are recognized by the WSM as the byte/word program setup. 12.The clear block lock-bits operation simultaneously clears all block lock-bits. P/N:PM0990 MX26L12811MC 8 REV. 1.0, OCT. 29, 2003 ...
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... NOTE: 1. A-1 is not used in either x8 or x16 mode when obtaining these identifier codes. Data is always given on the low byte in x16 mode (upper byte contains 00h). P/N:PM0990 MX26L12811MC Block 127 Reserved for Future Implementation Block 127 Lock Configuration Reserved for Future ...
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... To activate this mode, the two cycle "Silicon ID Read" command is requested. (The command sequence is il- lustrated in Table 3. Table 3. MX26L12811MC Silicon ID Codes and Verify Sector Protect Code Type Manufacture Code Device Code Block Lock Configuration ...
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... Yes RESERVED XSR.0 Notes: 1. After a Buffer-Write command, XSR indicates that a Write Buffer is available. 2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register. P/N:PM0990 MX26L12811MC Definition "1" "0" Ready Busy Error in Block Erasure or Successful Block ...
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... SR.7. Toggle OE update the status register. The CUI remains in read status regis- ter mode until a new command is issued. P/N:PM0990 MX26L12811MC WRITE TO BUFFER COMMAND To program the device, a Write to Buffer command is issue first. A variable number of bytes the buffer size, can be loaded into the buffer and written to the MTP device ...
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... R 15(A15 RCR.15 = READ MODE (RM Standard Word/Byte Reads Enabled (Default Page-Mode Reads Enabled RCR.14-1= RESERVED FOR FUTURE ENHANCEMENTS (R) P/N:PM0990 MX26L12811MC Notes Read mode configuration effects reads from the MTP array. Status register, query, and identifier reads support standard word/byte read cycles ...
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... VCC falls outside of the specified operat- ing ranges. The CUI latches commands issued by system software and is not altered by CE transitions, or WSM actions. Its state is read array mode upon power-up, after exit from power-down mode, or after VCC transitions below VLKO. P/N:PM0990 MX26L12811MC 14 REV. 1.0, OCT. 29, 2003 ...
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... Fill write buffer up to word count - Address=Address(es) within buffer range - Data=Data to be written Confirm Cycle - Issue Confirm Command - Address=Any address in block - Data=0xD0 Read Status Register See Status Register Flowchart P/N:PM0990 MX26L12811MC Start NO NO Write to Buffer D7=1? Time-Out ? YES YES Error-Handler Any Errors? ...
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... Figure 4. Status Register Flowchart - Set/Reset by WSM - Set by WSM - Reset by user - See Clear Status Register Command P/N:PM0990 MX26L12811MC Start Command Cycle - Issue Status Register Command - Address = any device address - Data = 0x70 Data Cycle - Read Status Register SR[7:0] No SR7 = ' Erase Suspend SR6 = '1' ...
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... FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR. SR. SR.4= 0 Byte/Word Program Successful P/N:PM0990 MX26L12811MC Bus Command Operation Write Setup Byte/ Word Program Addr=Location to Be Write Byte/Word Program Read (Note 1) Standby 1. Toggling OE (low to high to low) updates the status register ...
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... Figure 6. Block Erase Flowchart P/N:PM0990 MX26L12811MC Start Write 20H to Block Address Write Confirm D0H to Block Address Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Erase MTP Block(s) Completed 18 REV. 1.0, OCT. 29, 2003 ...
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... Figure 7. Set Block Lock-Bit Flowchart FULL STATUS CHECK PROCEDURE P/N:PM0990 MX26L12811MC Start Write 60H, Block Address Write 01H, Block Address Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See Above) NO Voltage Range Error SR.3=0 ? YES YES SR ...
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... Figure 8. Clear Lock-Bit Flowchart FULL STATUS CHECK PROCEDURE P/N:PM0990 MX26L12811MC Start Write 60H Write D0H Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See Above) NO Voltage Range Error SR.3=0 ? YES YES SR.4,5=1 ? Command Sequence Error ...
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... Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. P/N:PM0990 MX26L12811MC OPERATING RATINGS Commercial (C) Devices Ambient Temperature ( +150 ...
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... CMOS inputs are either VCC 0 GND 0.2 V. TTL inputs are either VIL or VIH . 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO , and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). P/N:PM0990 MX26L12811MC Notes Typ Max Unit ...
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... Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ). Input rise and fall times (10% tp 90%)<5ns. Figure 10. Transient Equivalent Testing Load Circuit Device Under Test NOTE: CL Includes Jig Capacitance Test Configuration C L (pF) VCCQ = VCC = 3.0 V-3 P/N:PM0990 MX26L12811MC VCCQ/2 Output TEST POINTS 1.3V 1N914 RL=3.3K ohm Out CL 23 REV. 1.0, OCT. 29, 2003 ...
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... When reading the MTP array a faster tGLQV (R15) applies. Non-array reads refer to status register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R14 (tAPA) will equal R1 (tAVQV). P/N:PM0990 MX26L12811MC VCC 3.0V-3.6V(3) VCCQ 3.0V-3.6V(3) Notes ...
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... Table 2). 2. For standard word/byte read operations, tAPA will equal tAVQV. 3. When reading the MTP array a faster tGLQV applies. Non-array reads refer to status register reads, query reads, or device identifier reads. P/N:PM0990 MX26L12811MC tAVAV Valid Address Valid Address Valid Address ...
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... Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL . 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. P/N:PM0990 MX26L12811MC Valid for All Speeds Notes ...
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... Table 1). a. VCC power-up and standby. b. Write block erase, write buffer, or program setup. c. Write block erase or write buffer confirm, or valid address and data. d. Automated erase delay. e. Read status register or query data. f. Write Read Array command. P/N:PM0990 MX26L12811MC AIN AIN tWHAX (tEHAX) ...
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... Parameter Symbol Parameter Description CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25 C, f=1.0MHz DATA RETENTION Parameter Minimum Pattern Data Retention Time P/N:PM0990 MX26L12811MC LIMITS MIN. TYP.(2) 2.0 218 210 0.8 10 MIN. -1.0V -1.0V -1.0V -100mA Test Set ...
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... ORDERING INFORMATION PLASTIC PACKAGE Part NO. MX26L12811MC-12 P/N:PM0990 MX26L12811MC Access Time Package type (ns) 120/25 44-SOP 29 REV. 1.0, OCT. 29, 2003 ...
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... PACKAGE INFORMATION P/N:PM0990 MX26L12811MC 30 REV. 1.0, OCT. 29, 2003 ...
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... REVISION HISTORY Revision No. Description 1.0 1. Removed "Advanced Information" from title 2. Typing error P/N:PM0990 MX26L12811MC Page P1 P12 31 Date OCT/29/2003 REV. 1.0, OCT. 29, 2003 ...
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... MX26L12811MC MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...