MBM29DL16XTE70PFTN Meet Spansion Inc., MBM29DL16XTE70PFTN Datasheet - Page 29

• Manufacturer Part Number: MBM29DL16XTE70PFTN
• Description: Flash Memory Cmos 16m 2m ? 8/1m ? 16 Bit Dual Operation
• Manufacturer: Meet Spansion Inc.

■ FUNCTIONAL DESCRIPTION
• Simultaneous Operation
• Read Mode
• Standby Mode
MBM29DL16XTD/BD have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A
The MBM29DL161TD/BD have two banks which contain
The MBM29DL162TD/BD have two banks which contain
The MBM29DL163TD/BD have two banks which contain
The MBM29DL164TD/BD have two banks which contain
The simultaneous operation can not execute multi-function mode in the same bank. “Simultaneous Operation
Table” shows combination to be possible for simultaneous operation. (Refer to “(8) Bank-to-bank Read/Write
Timing Diagram” in ■TIMING DIAGRAM.)
*: An erase operation may also be supended to read from or program to a sector not being erased.
The MBM29DL16XTD/BD have two control functions which must be satisfied in order to obtain data at the
outputs. CE is the power control and should be used for a device selection. OE is the output control and should
be used to gate data to the output pins if a device is selected.
Address access time (t
access time (t
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t
power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”
There are two ways to implement the standby mode on the MBM29DL16XTD/BD devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
Under this condition the current consumed is less than 5 μA Max. During Embedded Algorithm operation, V
active current (I
of these standby modes.
Bank 1 (8KB × eight sectors) and Bank 2 (64KB × thirty-one sectors).
Bank 1 (8KB × eight sectors, 64KB × three sectors) and Bank 2 (64KB × twenty eight sectors).
Bank 1 (8KB × eight sectors, 64KB × seven sectors) and Bank 2 (64KB × twenty four sectors).
Bank 1 (8KB × eight sectors, 64KB × fifteen sectors) and Bank 2 (64KB × sixteen sectors).
Case
1
2
3
4
5
6
7
CE
CC2
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
) is required even CE = “H”. The device can be read with standard access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
Autoselect mode
Bank 1 Status
Program mode
Erase mode *
Read mode
Read mode
Read mode
Read mode
Retired Product DS05-20874-8E_July 12, 2007
Simultaneous Operation Table
ACC
-t
OE
15
time.) When reading out a data without changing addresses after
to A
19
) with zero latency.
MBM29DL16XTD/BD
Autoselect mode
Bank 2 Status
Program mode
Erase mode *
Read mode
Read mode
Read mode
Read mode
CE
) from either
CC
± 0.3 V.
-70/90
CC
29