ST92141 STMicroelectronics, ST92141 Datasheet - Page 96

• Manufacturer Part Number: ST92141
• Description: 8/16-bit Mcu For 3-phase Ac Motor Control
• Manufacturer: STMicroelectronics

ST92141 - EXTENDED FUNCTION TIMER (EFT)
7.3 EXTENDED FUNCTION TIMER (EFT)
7.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals ( input capture ) or generation of up to two out-
put waveforms ( output compare and PWM ).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the
prescaler.
7.3.2 Main Features
The Block Diagram is shown in
96/179
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
– ICI: Timer Input capture interrupt.
– OCI: Timer Output compare interrupt.
– TOI: Timer Overflow interrupt.
– EFTI: Timer Global interrupt (replaces ICI,
Programmable prescaler: INTCLK divided by 2,
4 or 8.
Overflow status flag and maskable interrupts
External clock input (must be at least 4 times
slower than the INTCLK clock speed) with the
choice of active edge
Output compare functions with
Input capture functions with
Pulse width modulation mode (PWM)
One pulse mode
5 alternate functions on I/O ports*
Up to 3 separate Timer interrupts or a global
interrupt (depending on device) mapped on
external interrupt channels:
9
OCI and TOI).
Figure
53.
INTCLK
Table 21. EFT Pin Naming conventions
*Note 1: Some external pins are not available on
all devices. Refer to the device pin out description.
*Note 2: Refer to the device interrupt description,
to see if a single timer interrupt is used, or three
separate interrupts.
7.3.3 Functional Description
7.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running counter and its associated
16-bit registers:
Counter Registers
Alternate Counter Registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Control
peats every 131.072, 262.144 or 524.288 INTCLK
cycles depending on the CC1 and CC0 bits.
Function
Input Capture 1 -
ICAP1
Input Capture 2 -
ICAP2
Output Compare 1 -
OCMP1
Output Compare 2 -
OCMP2
– Counter High Register (CHR) is the most sig-
– Counter Low Register (CLR) is the least sig-
– Alternate Counter High Register (ACHR) is the
– Alternate Counter Low Register (ACLR) is the
nificant byte (MSB).
nificant byte (LSB).
most significant byte (MSB).
least significant byte (LSB).
Bits. The value in the counter register re-
page
EFT0
ICAPA0
ICAPB0
OCMPA0 OCMPA1 OCMPAn
OCMPB0 OCMPB1 OCMPBn
98).
EFT1
ICAPA1
ICAPB1
Table 22 Clock
EFTn
ICAPAn
ICAPBn