ST92141 STMicroelectronics, ST92141 Datasheet
ST92141
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ST92141 Summary of contents
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... Debugger Emulators with Real-Time Operating System available from Third Parties October 2001 DEVICE SUMMARY DEVICE ST92P141 Tools, including ST92E141 Archiver, and Hardware ST92T141 ST92141 PSDIP32 SO34 Shrink CSDIP32W Program RAM Memory PACKAGE (Bytes) (Bytes) PSDIP32/ 16K FASTROM 512 SO34 16K EPROM ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Note: The DMA features of the ST9+ core are not used by the on-chip peripherals of the ST92141. This multiple bus architecture makes the ST9 fam- ily devices highly efficient for accessing on and off- chip memory and fast exchange of data with the on-chip peripherals ...
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... For additional security, watchdog function can be enabled by hardware using a specific pin. ST92141 - GENERAL DESCRIPTION 1.1.8 Standard Timer The standard timer includes a programmable 16- bit down-counter and an associated 8-bit prescaler with Single and Continuous counting modes. ...
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... ST92141 - GENERAL DESCRIPTION Figure 1. ST92141 Block Diagram EPROM/ FASTROM 16K RAM 512 bytes Register File 256 bytes 8/16-bit CPU NMI WKUP[3:0] Interrupt INT0 Management INT6 ST9+ CORE OSCIN OSCOUT RCCU + LVD RESET INTCLK CK_AF ICAP1 OCMP1 EF TIMER ICAP2 OCMP2 EXTCLK STIN ...
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... PIN DESCRIPTION SCK/STIN/WKUP3/P3.2 STOUT/SSN/P3.3 EXTRG/OCMP2/P3.4 INT6/OCMP1/P3.5 ICAP1/WKUP2/P3.6 INTCLK/AIN7/P5.7 CK_AF/AIN6/P5.6 AIN3/EXTCLK/WDOUT/P5.3 AIN2/INT0/WDIN/P5.2 SCK/STIN/WKUP3/P3.2 STOUT/SSN/P3.3 EXTRG/OCMP2/P3.4 INT6/OCMP1/P3.5 ICAP1/WKUP2/P3.6 INTCLK/AIN7/P5.7 CK_AF/AIN6/P5.6 AIN3/EXTCLK/WDOUT/P5.3 AIN2/INT0/WDIN/P5.2 ST92141 - GENERAL DESCRIPTION MOSI/P3.0 MISO/P3 AIN5/P5.5 AIN4/P5 PSDIP32/CSDIP32W Package MOSI/P3.0 MISO/P3.1 N. AIN5/P5.5 AIN4/P5 ...
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... ST92141 - GENERAL DESCRIPTION Table 1. Power Supply Pins Name Function Programming voltage for V EPROM/OTP devices. Must be PP connected user mode. SS Main power supply voltage ( 10% (2 pins internally connected) Digital Circuit Ground (2 pins in ternally connected) Analog V of the Analog to Digit- ...
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... Schmitt trigger (High Hysteresis) Port 5.2 Schmitt trigger (Standard Hysteresis) Port 5[7:3] Schmitt trigger (Standard Hysteresis) Legend Open Drain; HC= High current ST92141 - GENERAL DESCRIPTION 1.2.2 I/O Port Reset State I/Os are reset asynchronously as soon as the RE- SET pin is asserted low. All I/Os are forced by the Reset in "floating input" configuration mode. ...
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... ST92141 - GENERAL DESCRIPTION Table 4. ST92141 Alternate functions Port General Purpose I/O Name SDIP32 PSO34 P3.0 2 P3.1 3 P3.2 4 P3.3 5 P3.4 6 P3.5 7 P3.6 8 All ports useable for general pur- P5.0 23 pose I/O (input, output or bidi- rectional) P5.1 22 P5.2 16 P5.3 15 P5.4 14 P5.5 13 P5.6 12 P5.7 11 How to configure the I/O ports To configure the I/O ports, use the information in Table 3 ...
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... AF: STIN, Port: P3.2, I/O Note: Schmitt trigger. Write the port configuration bits: P3C2.2=1 P3C1.2=0 P3C0.2=1 or P3C2.2=0 P3C1.2=0 P3C0.2=1 ST92141 - GENERAL DESCRIPTION Enable the Standard Timer input by software as described in the STIM chapter. Example 2: Standard Timer output AF: STOUT, Port: P3.3 Write the port configuration bits (for AF output push-pull): P3C2.3=0 P3C1 ...
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... ST92141 - GENERAL DESCRIPTION 1.3 MEMORY MAP 1.3.1 Memory Configuration The Program memory space of the ST92141, 16K bytes of directly addressable on-chip memory, is fully available to the user. The first 256 memory locations from address 0 to FFh hold the Reset Vector, the Top-Level (Pseudo Non-Maskable) interrupt, the Divide by Zero Trap ...
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... REGISTER MAP The following pages contain a list of ST92141 reg- isters, grouped by peripheral or function. Table 6. Common Registers Function or Peripheral ADC WDT I/O PORTS EXTERNAL INTERRUPT RCCU ST92141 - GENERAL DESCRIPTION Be very careful to correctly program both: – The set of registers dedicated to a particular function or peripheral. ...
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... ST92141 - GENERAL DESCRIPTION Table 7. Group F Pages Resources available on the ST92141 devices: Register 0 2 R255 Res. R254 Res. PORT R253 3 R252 WCR R251 Res. R250 WDT R249 R248 R247 R246 Res. PORT R245 EXT INT R244 R243 R242 Res. R241 Res. R240 ...
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... Port R245 5 R246 R240 R241 7 SPI R242 R243 R240 R241 11 STIM R242 R243 ST92141 - GENERAL DESCRIPTION Register Description Name CICR Central Interrupt Control Register FLAGR Flag Register RP0 Pointer 0 Register RP1 Pointer 1 Register PPR Page Pointer Register MODER Mode Register USPHR ...
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... ST92141 - GENERAL DESCRIPTION Page Reg. Block No. (Decimal) R240 R241 R242 MMU R243 21 R244 R248 R249 R245 EM R246 R240 R241 R242 R243 R244 R245 R246 R247 28 EFT R248 R249 R250 R251 R252 R253 R254 R255 R248 R249 R250 R251 48 IMC R252 R253 ...
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... R250 R251 R252 R253 R254 R255 Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details. ST92141 - GENERAL DESCRIPTION Register Description Name TCPTH Tacho Capture Register High TCPTL Tacho Capture Register Low ...
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... ST92141 - DEVICE ARCHITECTURE 2 DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 address- ing modes are available. Four independent buses are controlled by the ...
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... E SYSTEM REGISTERS 224 223 ST92141 - DEVICE ARCHITECTURE Figure 5. Page Pointer for Group F mapping PAGES R255 R240 R234 224 R224 GENERAL PURPOSE REGISTERS VA00432 R0 R195 (R0C3h) (1100) (0011 PAGE 63 PAGE 5 PAGE 0 ...
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... ST92141 - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h and R11100111b represent the same register (see Figure 6) ...
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... CE bit in the TCR Register (only in devices featur- ing the MFT Multifunction Timer) in order to enable the Timers when both bits are set. This bit is set af- ter the Reset cycle. ST92141 - DEVICE ARCHITECTURE Table 10 Sys- Note MFT is not included in the ST9 device, then this bit has no effect. ...
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... ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the CPU to its original status. ...
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... Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruc- tion selects the single 16-register group mode and ST92141 - DEVICE ARCHITECTURE specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block ...
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... ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions ...
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... r15 ST92141 - DEVICE ARCHITECTURE Figure 8. Pointing to two groups of 8 registers BLOCK NUMBER REGISTER POINTER 0 set by: srp #2 instruction points to: addressed by BLOCK 7 GROUP 1 addressed by BLOCK 2 REGISTER GROUP REGISTER FILE 31 REGISTER F POINTER 0 30 & ...
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... ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. ...
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... Interrupts When entering an interrupt, the PC and the Flag Register are pushed onto the System Stack. If the ENCSR bit in the EMR2 register is set, then the ST92141 - DEVICE ARCHITECTURE Code Segment Register is also pushed onto the System Stack. – Subroutine Calls When a call instruction is executed, only the PC ...
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... ST92141 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined 7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) Reset value: undefined ...
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... Mbytes. This address space is ar- ranged as 64 segments of 64 Kbytes; each seg- ment is again subdivided into four 16 Kbyte pages. ST92141 - DEVICE ARCHITECTURE The mapping of the various memory areas (inter- nal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally ...
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... ST92141 - DEVICE ARCHITECTURE 2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. ...
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... DPR1 are modified by the instruction, unpredicta- ble behaviour could result. MMU registers DPR2 DPR3 bits 14 LSB 22-bit physical address ST92141 - DEVICE ARCHITECTURE DPR0: from 0000h to 3FFFh; DPR1: from 4000h to 7FFFh; DPR2: from 8000h to BFFFh; DPR3: from C000h to FFFFh. Figure 12). 16-bit virtual address 33/179 1 ...
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... ST92141 - DEVICE ARCHITECTURE ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ISR, and DMASR. ...
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... Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh. ST92141 - DEVICE ARCHITECTURE DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2 ...
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... ST92141 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are imple- mented, and bits 6 and 7 are reserved ...
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... MMU REGISTERS (Cont’d) Figure 14. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR ST92141 - DEVICE ARCHITECTURE 4M bytes 16K 16K 16K 64K 64K 16K 64K 3FFFFFh 294000h 240000h 23FFFFh 20C000h 200000h 1FFFFFh 040000h 03FFFFh 030000h 020000h 010000h 00C000h 000000h ...
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... ST92141 - DEVICE ARCHITECTURE 2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries ...
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... Warning . Although the Divide by Zero Trap oper- IRET INSTRUCTION ates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically result it must be regarded as a subroutine, and the service routine must end with the RET instruction VR001833 (not IRET). ST92141 - INTERRUPTS 39/179 1 ...
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... ST92141 - INTERRUPTS 3.2.2 Segment Paging Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compati- bility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, the CPU works in original ST9 compatibility mode. For the duration of the inter- ...
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... CPL. No trace is kept of its value during the ISR. If other requests are issued during the inter- rupt service routine, once the global CICR.IEN is re-enabled, they will be acknowledged regardless of the interrupt service routine’s priority. This may cause undesirable interrupt response sequences. ST92141 - INTERRUPTS 41/179 1 ...
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... ST92141 - INTERRUPTS ARBITRATION MODES (Cont’d) Examples In the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. Figure 17. Simple Example of a Sequence of Interrupt Requests with: - Concurrent mode selected and - IEN unchanged by the interrupt routines ...
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... INT 2 CPL = 7 INT 3 ei CPL = 7 ei INT 4 CPL = 7 ei ST92141 - INTERRUPTS INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INT 2 CPL = 7 INT 3 CPL = 7 INT 5 CPL = 7 ...
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... ST92141 - INTERRUPTS ARBITRATION MODES (Cont’d) 3.5.2 Nested Mode The difference between Nested mode and Con- current mode, lies in the modification of the Cur- rent Priority Level (CPL) during interrupt process- ing. The arbitration phase is basically identical to Con- current mode, however, once the request is ac- ...
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... INT2 CPL=3 ei INT 4 INT 4 CPL=4 CPL=4 ei ST92141 - INTERRUPTS contains a simple example, showing that contains a more complex example INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6 ...
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... ST92141 - INTERRUPTS 3.6 EXTERNAL INTERRUPTS The standard ST9 core contains 8 external inter- rupts sources grouped into four pairs. Table 12. External Interrupt Channel Grouping External Interrupt none INT6 none none none none none INT0 Each source has a trigger control bit TEA0,..TED1 (R242,EITR.0,..,7 Page 0) to select triggering on the rising or falling edge of the external pin. If the Trigger control bit is set to “ ...
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... VECTOR “1” Priority level “0” Mask bit IMD0 * ID1S VECTOR “1” Priority level “0” Mask bit IMD1 ST92141 - INTERRUPTS PL2A PL1A 0 INT A0 request IMA0 Pending bit IPA0 PL2A PL1A ...
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... ST92141 - INTERRUPTS 3.7 TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high (the reset condition) the source is the external pin NMI. ...
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... INTCLK is running (i.e. when the ST92141 is not in Stop Mode). – a NMI event is immediately acknowledged in the IMC. The ST92141 can be either in Stop or in duction Motor Controller (IMC) and the Wake Up Management Unit (WUIMU). The IMC Controller processes the NMI Input and ...
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... The WUIMU can manage External-Inter- rupt/ Wake up lines. Usually, only a subset of these 16 lines is used. In the ST92141, 4 lines out of 16 are available as external lines (WKUP0/1/2/3) but the Pending and Mask bits of the unused lines (WKUP4 to WKUP 15) are also accessible by software (refer to tion 3 ...
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... ST92141 - INTERRUPTS cycles (DIVWS and MUL instructions for other instructions. For a non-maskable Top Level interrupt, the re- ...
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... ST92141 - INTERRUPTS 3.11 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit enables the 16-bit Multifunction Timer pe- ripheral. 0: MFT disabled 1: MFT enabled Bit 6 = TLIP: Top Level Interrupt Pending ...
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... Bit 7 = IMD1: INTD1 Interrupt Mask Bit 6 = IMD0: INTD0 Interrupt Mask Bit 5 = IMC1: INTC1 Interrupt Mask Bit 4 = IMC0: INTC0 Interrupt Mask ST92141 - INTERRUPTS Bit 3 = IMB1: INTB1 Interrupt Mask Bit 2 = IMB0: INTB0 Interrupt Mask Bit 1 = IMA1: INTA1 Interrupt Mask Bit 0 = IMA0: INTA0 Interrupt Mask These bits are set and cleared by software ...
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... ST92141 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h TLTEV TLIS IAOS EWEN Bit 7:4 = V[7:4]: Most significant nibble of External Interrupt Vector . These bits are not initialized by reset. For a repre- ...
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... Note: The number of available pins is device de- pendent. Refer to the device pinout description. WKUP[15:8] WUTRH WUTRL WUPRH WUPRL WUMRH WUMRL SW SETTING 1 0 WUCTRL TO RCCU - Stop Mode Control ST92141 - INTERRUPTS TRIGGERING LEVEL REGISTERS PENDING REQUEST REGISTERS MASK REGISTERS INT7 (not connected) TO CPU INTD1 - External Interrupt Channel 55/179 1 ...
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... ST92141 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 3.12.3 Functional Description 3.12.3.1 Interrupt Mode To configure the 16 wake-up lines as interrupt sources, use the following procedure: 1. Configure the mask bits of the 16 wake-up lines (WUMRL, WUMRH). 2. Configure the triggering edge registers of the wake-up lines (WUTRL, WUTRH). ...
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... Programming Considerations The following paragraphs give some guidelines for designing an application program. ST92141 - INTERRUPTS 3.12.4.1 Procedure for Entering/Exiting STOP mode 1. Program the polarity of the trigger event of external wake-up lines by writing registers WUTRH and WUTRL ...
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... ST92141 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 3.12.4.2 Simultaneous Setting of Pending Bits It is possible that several simultaneous events set different pending bits. In order to accept subse- quent events on external wake-up/interrupt lines necessary to clear at least one pending bit: this operation allows a rising edge to be generated on the INTD1 line (if there is at least one more pend- ing bit set and not masked) and so to set EIPR ...
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... EIPR - R243, Page 0). 4. Remove the mask on INTD1 (bit EIMR.7=1). Bit 0 = WKUP-INT: Wakeup Interrupt. This bit is set and cleared by software. 0: The 16 external wakeup lines can be used to generate interrupt requests 1: The 16 external wake-up lines to work as wake- up sources for exiting from STOP mode ST92141 - INTERRUPTS 59/179 1 ...
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... ST92141 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH (WUMRH) R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) 7 WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 Bit 7:0 = WUM[15:8]: Wake-Up Mask bits. If WUMx is set, an interrupt on channel INTD1 and/or a wake-up event (depending on ID1S and WKUP-INT bits) are generated if the correspond- ing WUPx pending bit is set ...
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... No Wake-up Trigger event occurred 1: Wake-up Trigger event occurred Note: To avoid losing a trigger event while clear- ing the pending bits recommended to use read-modify-write BAND) to clear them. ST92141 - INTERRUPTS WUP5 WUP4 WUP3 WUP2 WUP1 instructions (AND, ...
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... In ST9 devices with external memory, the EM reg- isters (External Memory Registers) are used to configure the external memory interface. In the ST92141, only the BSZ, ENCSR and DPREM bits must be programmed. All other bits in these regis- ters must be left at their reset values. EM REGISTER 1 (EMR1) ...
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... CLOCK1 CK_AF CK_AF pin ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) put clock to the programmable Phase Locked Loop frequency multiplier, which is capable of mul- tiplying the clock frequency by a factor 14; the multiplied clock is then divided by a pro- grammable divider factor this ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 27. ST92141 Clock Distribution Diagram (settings given for 5MHz crystal & 25MHz lnternal clock) N=1,4,6,8,10,12,14,16 Conversion time N X 138 X INTCLK A/D EFT P5.7 Baud Rate Generator SCK Master 1/N N=2,4,16,32 SCK Slave (Max INTCLK/2) SPI DIV2=1 5 MHz Quartz 0 Oscillator ...
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... WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode. XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected. ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) – CLK_FLAG (Clock Flag Register) This is a Paged Register (R242, Page 55). ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 5.3.1 PLL Clock Multiplier Programming The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condi- tion), CLOCK2, is equal to CLOCK1 divided by two; if DIV2 is reset, CLOCK2 is identical to CLOCK1 ...
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... INTCLK EXAMPLE 2.2*10/2 XTAL=4.4 MHz = 11MHz ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) tal oscillator will be stopped automatically on en- tering WFI if the WFI_CKSEL bit has been set. It should be noted that selecting a non-existent CK_AF clock source is impossible, since such a selection requires that the auxiliary clock source be actually present and selected ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 30. Example of Low Power Mode programming PROGRAM FLOW Begin DIV2 XTSTOP = 0 CSU_CKSEL = 0 MX(1:0) DX2-0 000 WAIT CSU_CKSEL Wait for the WFI_CKSEL PLL locking (LOCK->1) XTSTOP LPOWFI User’s Program WFI Interrupt WFI status Interrupt Routine ...
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... CPUCLK is not prescaled, and is equal to INTCLK; in all other cases, the internal clock is prescaled by the value of these three bits plus one. ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTER (CLKCTL) R240 - Read Write Register Page: 55 Reset Value: 0000 0000 (00h) ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS (Cont’d) CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 0100 1000 after a Watchdog Reset Reset Value: 0010 1000 after a Software Reset Reset Value: 0000 1000 after a Power-On Reset ...
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... Figure 31. RCCU General Timing STOP (*) request External RESET Xtal clock Multiplier clock Internal reset INTCLK (*) WUIMU (**) +/- 1 T Xtal ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) Table 15. PLL Multiplication Factors MX1 DX2 DX1 DX0 0 Table 16. Divider Configuration for DX2 0 0 for divider ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 32. RCCU Timing during STOP (CK_AF System Clock) STOP request (*) Xtal clock CK_AF clock INTCLK 20478 x T (**) Xtal Exit from RESET (*) from WUIMU (**) +/- 1 T Xtal Figure 33. Low Power WFI Mode with a Stopped Quartz Oscillator ...
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... CPU will be reset when the Watchdog times out or when an external reset is applied. Figure 34. Crystal Oscillator CRYSTAL CLOCK ST9 OSCOUT OSCIN C L1 1M* *Recommended for oscillator stability ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) Table 17. Crystal Specification (5V) Rs max C L1 (ohm) Freq.= 3 MHz Freq.= 4 MHz Freq.= ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) 5.6 RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: – A Hardware reset, initiated by a low level on the Reset pin. – A Software reset, initiated by a HALT instruction (when enabled). ...
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... Reset pin. The device is certain to re- set if a negative pulse of more than 20µs is ap- ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) plied. When the reset pin goes high again, a delay 4µs will elapse before the RCCU detects this rising front ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) 5.7 STOP MODE Under control of the Wake-up Interrupt Manage- ment Unit (WUIMU), the Reset/Stop Manager can also stop all oscillators without resetting the de- vice. In Stop Mode all context information will be pre- served. During this condition the internal clock will be frozen in the high state ...
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... Figure 39. Oscillator Start-up sequence on Exit from Stop Mode V MAX DD V MIN DD OSCIN OSCOUT STOP disactivation 5.1 ms (*) < T INTCLK (*) with 4MHz quartz and RCCU programmed with XT_STOP bit = 1 when read ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) T START-UP < 5 INTCLK START-UP 77/179 1 ...
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... ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU) 5.8 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below value. This means that it secures the power-up as well as the power-down keeping the ST9 in reset ...
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... F9h P2C1 F8h P2C0 F7h Reserved F6h P1C2 F5h P1C1 F4h P1C0 F3h Reserved F2h P0C2 F1h P0C1 F0h P0C0 ST92141 - I/O PORTS GROUP F GROUP F PAGE 3 PAGE 43 P7DR P9DR R255 P7C2 P9C2 R254 P7C1 P9C1 R253 P7C0 P9C0 R252 P6DR P8DR R251 ...
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... ST92141 - I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROM- less devices, and can be redefined under software control ...
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... BID OUT OUT HI-Z TTL TTL TTL CMOS (or Schmitt (or Schmitt (or Schmitt (or Schmitt Trigger) Trigger) Trigger) Trigger) ST92141 - I/O PORTS PxC20 PxC10 PxC00 OUT AF OUT HI TTL TTL TTL (or Schmitt (or Schmitt (or Schmitt ...
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... ST92141 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 43. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 44. Input Configuration I/O PIN TRISTATE OUTPUT SLAVE LATCH ...
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... Function Output: (Figure 47) – The Output Buffer is turned Open-Drain or Push-Pull configuration. ST92141 - I/O PORTS – The data present on the I/O pin is sampled into the Input Latch at the beginning of the execution of the instruction. – The signal from an on-chip function is allowed to load the Output Slave Latch driving the I/O pin. ...
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... ST92141 - I/O PORTS 6.5 ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 6.5.1 Pin Declared as I/O A pin declared as I/O, is connected to the I/O buff- er. This pin may be an Input, an Output bidi- rectional I/O, depending on the value stored in (PxC2, PxC1 and PxC0) ...
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... HW0SW1 MUX WDGEN 1 Pin not present on some ST9 devices ST92141 - TIMER/WATCHDOG (WDT) The main WDT registers are: – Control register for the input, output and interrupt logic blocks (WDTCR) – 16-bit counter register pair (WDTHR, WDTLR) – Prescaler register (WDTPR) The hardware interface consists five sig- nals: – ...
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... ST92141 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.2 Functional Description 7.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to section 7.1.3.1 on page 87. The WDIN Input pin can be used in one of four modes: – Event Counter Mode – Gated External Input Mode – Triggerable Input Mode – ...
Page 87
... PWM signals by modifying the status of the WROUT pin between End of Count events, based on software counters decre- mented by the Timer Watchdog interrupt. ST92141 - TIMER/WATCHDOG (WDT) 7.1.3 Watchdog Timer Operation This mode is used to detect the occurrence of a software fault, usually generated by external inter- ...
Page 88
... ST92141 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the constant and counting re- starts from the preset value. ...
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... WDG = Watchdog function SW TRAP = Software Trap Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0 interrupts), only the INTA0 interrupt is taken into account. ST92141 - TIMER/WATCHDOG (WDT) Figure 51. Interrupt Sources INT0 below, shows all NMI ...
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... ST92141 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register Three additional control bits are mapped in the fol- lowing registers on Page 0: Watchdog Mode Enable, (WCR ...
Page 91
... Resetting this bit via software enters the Watch- dog mode. Once reset, it cannot be set anymore by the user program. At System Reset, the Watch- dog mode is disabled. ST92141 - TIMER/WATCHDOG (WDT) Note: This bit is ignored if the Hardware Watchdog option is enabled by pin HW0SW1 (if available). EXTERNAL INTERRUPT VECTOR REGISTER ...
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... ST92141 - STANDARD TIMER (STIM) 7.2 STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip- tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals de- scribed may not be connected to external pins. For the list of STIM pins present on the particular ST9 device, refer to the pinout description in the first section of the data sheet ...
Page 93
... Standard Timer Input STIN) Bits INMD2, INMD1 and INEN are used to select the input modes. The Input Enable (INEN) bit ena- ST92141 - STANDARD TIMER (STIM) bles the input mode selected by the INMD2 and INMD1 bits. If the input is disabled (INEN="0"), the values of INMD2 and INMD1 are not taken into ac- count ...
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... ST92141 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 7.2.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the I/O pin. Square Wave Output Mode (OUTMD1 = “ ...
Page 95
... When reading the STP register, the returned value corresponds to the programmed data instead of the current data. 00h: No prescaler 01h: Divide by 2 FFh: Divide by 256 ST92141 - STANDARD TIMER (STIM) STANDARD (STC) R243 - Read/Write Register Page: 11 Reset value: 0001 0100 (14h) ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) 7.3 EXTENDED FUNCTION TIMER (EFT) 7.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals ( input capture ) or generation two out- put waveforms ( output compare and PWM ) ...
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... OVERFLOW EXTCLK DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 ICIE OCIE TOIE FOLV2 FOLV1 ETOI EEFTI TOI EFTI ST92141 - EXTENDED FUNCTION TIMER (EFT) ST9 INTERNAL BUS MCU-PERIPHERAL INTERFACE OUTPUT OUTPUT COMPARE COMPARE REGISTER REGISTER TIMER INTERNAL BUS 16 ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MSB At t0 Other instructions Returns the buffered Read LSB At t0 +Dt LSB value at t0 Sequence completed The user must read the MSB first, then the LSB value is buffered automatically ...
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... TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 56. Counter Timing Diagram, INTCLK divided by 8 INTCLK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF ST92141 - EXTENDED FUNCTION TIMER (EFT) INTCLK FFFD FFFE FFFF 0000 FFFC FFFD FFFC FFFD 0001 0002 0003 ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 7.3.3.3 Input Capture In this section, the index may The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition detected by the ICAP i pin (see figure 5) ...
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... COUNTER Figure 58. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive edge is rising edge. Note: A ST92141 - EXTENDED FUNCTION TIMER (EFT) EDGE DETECT ICIE CIRCUIT1 ICF1 IC1R FF02 (Control Register 1) CR1 IEDG1 (Status Register) SR ICF2 ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 7.3.3.4 Output Compare In this section, the index may This function can be used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – ...
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... CIRCUIT 16-bit 16-bit OC2R OC1R Figure 60. Output Compare Timing Diagram, Internal Clock Divided by 2 OUTPUT COMPARE REGISTER COMPARE REGISTER LATCH OCFi AND OCMPi PIN (OLVLi=1) ST92141 - EXTENDED FUNCTION TIMER (EFT) OC1E OC2E CC1 (Control Register 2) (Control Register 1) OCIE OLVL2 OCF1 OCF2 ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 7.3.3.5 Forced Compare Mode In this section i may represent The following bits of the CR1 register are used: FOLV2 FOLV1 OLVL2 When the FOLV i bit is set, the OLVL i bit is copied to the OCMP i pin. The OLVL i bit has to be toggled in order to toggle the OCMP i pin when it is enabled ( bit=1) ...
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... Figure 62. Pulse Width Modulation Mode Timing 34E2 FFFC FFFD FFFE COUNTER OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 ST92141 - EXTENDED FUNCTION TIMER (EFT) Where: – Desired output compare period (seconds) – = Internal clock frequency INTCLK – CC1-CC0 = Timer clock prescaler The Output Compare 2 event causes the counter ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 7.3.4 Interrupt Management The interrupts of the Extended Function Timer are mapped on the eight external interrupt channels of the microcontroller (refer to the “Interrupts” chap- ter). Depending on device specification, one of the fol- lowing configurations can occur: – ...
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... L6 ld r1,R245 ; Insert your code here jx L6 L7: pop R234 iret ST92141 - EXTENDED FUNCTION TIMER (EFT) registers must be accessed if the corresponding flag is set not necessary to access the SR register between these instructions, but it can done. ; Save current page ; Set EFT page ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) 7.3.5 Register Description Each Timer is associated with three control and one status registers, and with six pairs of data reg- isters (16-bit values) relating to the two input cap- tures, the two output compares, the counter and the alternate counter ...
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... This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. 7 MSB ST92141 - EXTENDED FUNCTION TIMER (EFT) ALTERNATE COUNTER (ACHR) R246 - Read Only Register Page: 28 ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) OUTPUT COMPARE 1 HIGH (OC1HR) R248 - Read/Write Register Page: 28 Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT ...
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... Interrupt is inhibited timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare effect. ST92141 - EXTENDED FUNCTION TIMER (EFT) 1: Forces the OLVL2 bit to be copied to the OCMP2 pin. Bit 3 = FOLV1 Forced Output Compare effect. ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) CONTROL REGISTER 2 (CR2) R253 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Enable. 0: Output Compare 1 function is enabled, but the OCMP1 pin is a general I/O ...
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... OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) reg- ister. Bit 2-0 = Reserved, forced by hardware to 0. ST92141 - EXTENDED FUNCTION TIMER (EFT) CONTROL REGISTER 3 (CR3) R255 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) ...
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... ST92141 - EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Table 23. Extended Function Timer Register Map Address Register 7 Name (Dec.) IC1HR MSB R240 Reset Value x IC1LR MSB R241 Reset Value x IC2HR MSB R242 Reset Value x IC2LR MSB R243 Reset Value x CHR ...
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... EXTENDED FUNCTION TIMER (Cont’d) Table 24. Extended Function Timer Page Map Timer number EFT0 ST92141 - EXTENDED FUNCTION TIMER (EFT) Page (hex) 1C 115/179 9 ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) 7.4 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) 7.4.1 Introduction The IMC controller is designed for variable speed motor control applications. Three PWM outputs are available for controlling a three-phase motor drive. Rotor speed feedback is provided by captur- ing a tachogenerator input signal. ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) 7.4.3.1 Input and Output pins – Input Pin TACHO: Signal input from a tachogenerator for measuring the rotor speed. NMI: Input signal for disabling the IMC output and sending an interrupt request to the ST9 core. – ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) If the 11-bit Compare register value is greater than the extended Compare 0 Register (the 11 set to ‘0’), the corresponding PWM output signal is held at ‘1’. Figure 65. Zerocentered PWM Waveforms (Compare 0 Register = ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) PWM signals generation in Classical mode In this mode, each of the three PWM signals set to ‘0’ when the PWM Counter reaches, in up-count- ing, the corresponding 11-bit Compare register value and they are set to ‘1’ when the PWM Coun- ter is cleared ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) Repetition Down-Counter Both in Zerocentered and Classical working mode, the four Compare registers (one Compare 0 and three for the U, V and W phases) are updated when the PWM counter value is zero and the 8-bit ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) Figure 68. Dead Time waveforms with delay greater than the negative PWM pulse Figure 69. Dead Time waveforms with delay greater than the positive PWM pulse Delay Delay ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) 7.4.3.5 Polarity Selection The Polarity Selection performs a logical comple- ment of the input signals (Uh, Ul, Vh, Vl, Wh, Wl) as programmed in the Polarity Selection register. 7.4.3.6 Interrupts The IMC controller generates 8 interrupt requests and 1 NMI. Each interrupt request has a separate vector address ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) 7.4.5.2 IMC Software Operating mode In this operating mode, the Repetition register and any Compare register can be independently up- dated by software by setting the SDT bit in the PCR2 register (this bit will be reset by hardware) and the corresponding enable bit in the same reg- ister ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) 7.4.7 NMI management Figure 71 shows how the external input NMI signal is managed by the IMC peripheral. After an ST9 reset, the NMIE bit in the PCR1 reg- ister is cleared, which means that NMI signal com- ing from the external pin is sent, as is, to the ST9 core without affecting the IMC peripheral ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) 7.4.8 Register Description TACHO CAPTURE REGISTER HIGH (TCPTH) R240 - Read Only Register Page: 51 Reset Value: undefined 7 TCH7 TCH6 TCH5 TCH4 TCH3 TCH2 TCH1 TCH0 Bit 7:0 = TCH[7:0] Most Significant Byte of Tacho Capture register. ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) INTERRUPT PENDING REGISTER (IPR) R243 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h) 7 CM0 CPT OTC ADT ZPC Bit 7 = CM0: Compare 0 of PWM pending bit. This bit is set by hardware when the PWM counter reaches the value in the Compare 0 register while CM0E=1 ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) TACHO PRESCALER REGISTER (TPRSH) R244 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h) 7 TPRH - - - - 3 Bit 7:4 = Reserved. Bit 3:0 = TPRH[3:0] Most Significant Bits of tacho prescaler value (N). TACHO PRESCALER REGISTER LOW (TPRSL) R245 - Read/Write ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) COMPARE PHASE W PRELOAD REGISTER HIGH (CPWH) R248 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h) 7 CPWH CPWH CPWH CPWH CPWH Bit 7:0 = CPWH[7:0] Most Significant Byte of phase W preload value ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) COMPARE PHASE U PRELOAD REGISTER HIGH (CPUH) R252 - Read/Write Register Page: 51 Reset Value: 0000 0000 (00h) 7 CPUH CPUH CPUH CPUH CPUH Bit 7:0 = CPUH[7:0] Most Significant Byte of phase U preload value ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) PERIPHERAL CONTROL REGISTER 0 (PCR0) R248 - Read/Write Register Page: 48 Reset Value: 1000 0011 (83h) 7 DTE TCE PCE CTC CPC Bit 7 = DTE: Dead Time Counter Enable. 0: Stop and bypass the Dead Time counter 1: Enable the Dead Time counter Bit 6 = TCE: Tacho Counter Enable ...
Page 131
... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d)) PERIPHERAL CONTROL REGISTER 2 (PCR2) R250 - Read/Write Register Page: 48 Reset Value: 0000 0000 (00h) 7 GPIE RSE CWSE CVSE CUSE C0SE Bit 7 = GPIE: Global Peripheral Interrupt Enable. 0: Disable all IMC controller interrupts. ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) OUTPUT PERIPHERAL REGISTER (OPR) R252 - Read/Write Register Page: 48 Reset Value: 0000 0000 (00h) 7 OPE ODS Bit 7 = OPE: Output Port Enable. This bit can be set by software only if the NMI bit is cleared ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) DEAD TIME GENERATOR REGISTER (DTG) R254 - Read/Write Register Page: 48 Reset Value: 0011 1111 (3Fh DTG5 DTG4 DTG3 DTG2 DTG1 DTG0 Bit 7:6 = Reserved. Bit 5:0 = DTG[5:0] Dead time generator value (N) . The delay INTCLK period multiplied by 2. ...
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... ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) Table 27. IMC Controller Register Map Page 51 Register 7 Register Name No. R240 TCPTH TCH7 R241 TCPTL TCL7 R242 TCMP TCP7 R243 IPR CM0 R244 TPRSH - R245 TPRSL TPRL7 R246 CPRS CPR7 R247 ...
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... MSBit LSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) – MISO: Master In Slave Out pin – MOSI: Master Out Slave In pin – SCK: Serial Clock pin – SS: Slave select pin To use any of these alternate functions (input or output), the corresponding I/O port must be pro- grammed as alternate function output ...
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... ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 73. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS 1/2 ST9 PERIPHERAL CLOCK (INTCLK) 136/179 9 Internal Bus DR SPIF WCOL SPIE SPOE SPIS MSTR MASTER CONTROL ...
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... The MSTR and SPOE bits must be set (they remain set only if the SS pin is connected to a high level signal). ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit Sequence The transmit sequence begins when a byte is writ- ten the DR register ...
Page 138
... ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.5.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the PR register and SPR0 & SPR1 bits in the CR is not used for the data transfer. ...
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... Master SS Slave SS (CPHA=0) Slave SS (CPHA=1) ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) The master device applies data to its MOSI pin- clock edge before the capture clock edge. CPHA Bit is Set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe ...
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... ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 75. Data Clock Timing Diagram CPOL = 1 CPOL = 0 MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MISO MSBit (from master) MOSI MSBit (from slave) SS (to slave) CAPTURE STROBE Note: This figure should not be used as a replacement for parametric information ...
Page 141
... Step nd 2 Step ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low ...
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... ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.5.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – ...
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... Master MCU 5V SS ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con- nected and the slave has not written its DR regis- ter ...
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... ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.5.5 Interrupt Management The interrupt of the Serial Peripheral Interface is mapped on one of the eight External Interrupt Channels of the microcontroller (refer to the “Inter- rupts” chapter). Each External Interrupt Channel has: – A trigger control bit in the EITR register (R242 - Page 0), – ...
Page 145
... SCK can only work as input) 1: SPI alternate functions enabled (MISO, MOSI and SCK can work as input or output depending on the value of MSTR) ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) Note: To use the MISO, MOSI and SCK alternate functions (input or output), the corresponding I/O port must be programmed as alternate function output ...
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... ST92141 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SPSR) R242 - Read Only Register Page: 7 Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register ...
Page 147
... TRIGGER CONTROL LOGIC EXTERNAL TRIGGER CONTROL REG. ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) Conversion resolution is 8 bits, with ±1 LSB maxi- mum error in the input range between V analog V DD The converter uses a fully differential analog input configuration for the best noise immunity and pre- cision performance ...
Page 148
... ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) ANALOG TO DIGITAL CONVERTER (Cont’d) Single and continuous conversion modes are available. Conversion may be triggered by an ex- ternal signal or, internally, by the Multifunction Timer. Conversion Time The maximum conversion time is as follows: 138 * FDF * INTCLK The minimum sample time is: ...
Page 149
... Compare Results Register are used as flags, each of the four MSBs being associated with a threshold condition. Figure 79. A/D Trigger Source ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) Following a reset, these flags are reset. During normal ADC operation, the CRR bits are set, in or- der to flag an out of range condition and are auto- ...
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... ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) ANALOG TO DIGITAL CONVERTER (Cont’d) Figure 80. Application Example: Analog Watchdog used in Motorspeed Control 7.6.3 Interrupts The ADC provides two interrupt sources: – End of Conversion – Analog Watchdog Request The A/D Interrupt Vector Register (IVR) provides hardware generated flags which indicate the inter- rupt source, thus allowing automatic selection of the correct interrupt service routine ...
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... D2.4 D2.3 D2.2 Bit 7:0 = D2.[7:0]: Channel 2 Data CHANNEL 3 DATA REGISTER (D3R) R243 - Read/Write Register Page: 63 Reset Value: undefined 7 D3.7 D3.6 D3.5 D3.4 D3.3 D3.2 Bit 7:0 = D3.[7:0]: Channel 3 Data ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) CHANNEL 4 DATA REGISTER (D4R) R244 - Read/Write Register Page: 63 Reset Value: undefined 7 D4.7 D4.6 D4.5 D4.4 Bit 7:0 = D4.[7:0]: Channel 4 Data 0 D0.1 D0.0 CHANNEL 5 DATA REGISTER (D5R) R245 - Read/Write ...
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... ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) LOWER THRESHOLD REGISTERS (LTiR) The two Lower Threshold registers are used to store the user programmable lower threshold 8-bit values compared with the current conver- sion results, thus setting the lower window limit. ...
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... Not affected otherwise. These bits should be reset at the end of the “Out of Range” interrupt service routine. ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) Note: Any software reset request of the ICR, will also cause all the compare status bits to forced by hardware to zero, in order to prevent possible overwriting if an interrupt request occurs between reset and the Interrupt request software reset ...
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... ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) REGISTER DESCRIPTION (Cont’d) CONTROL LOGIC REGISTER (CLR) The Control Logic Register (CLR) manages the ADC’s logic. Writing to this register will cause the current conversion to be aborted and the autoscan logic to be re-initialized. CLR is programmable as ...
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... Bit 5 = ECI: End of Conversion Interrupt Enable. This bit masks the End of Conversion interrupt re- quest. 0: Mask End of Conversion interrupts 1: Enable End of Conversion interrupts ST92141 - ANALOG TO DIGITAL CONVERTER (ADC) Bit 4 = AWDI: Analog Watchdog Interrupt Enable . This bit masks or enables the Analog Watchdog interrupt request. 0: Mask Analog Watchdog interrupts 1: Enable Analog Watchdog interrupts Bit 3 = Reserved ...
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... ST92141 - ELECTRICAL CHARACTERISTICS 8 ELECTRICAL CHARACTERISTICS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V ...
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... LKA/D Note: (1) Unless otherwise stated, typical data are based on T duction. (2) Data based on characterization results - not tested in production. (3) For a description of the EMR1 Register - BSZ bit refer to the Device Configuration Registers Chapter. ST92141 - ELECTRICAL CHARACTERISTICS Comment Push Pull – 2mA OH (3) EMR1 Register - BSZ bit = 0 Psh Pull – ...
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... ST92141 - ELECTRICAL CHARACTERISTICS LOW VOLTAGE DETECTOR DC CHARACTERISTICS ( 10 40°C to +85°C, unless otherwise specified) – Symbol Parameter Reset release V LVDR Threshold Reset generation V LVDF Threshold (2) V Hysteresis LVDHyst I Supply Current DDLVD Note: (1) Unless otherwise stated, typical data are based on T duction ...
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... All I/O Ports are configured to a static value of VDD or VSS, external clock pin (OSCIN) is driven by square wave external clock. (1) Unless otherwise stated, typical data are based on T production. (2) CPU running with memory access, all peripherals switched off. ST92141 - ELECTRICAL CHARACTERISTICS Parameter INTCLK (2) ...
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... ST92141 - ELECTRICAL CHARACTERISTICS EXTERNAL INTERRUPT TIMING TABLE ( 10 40°C to +85°C, C – N° Symbol 1 TwINTLR Low Level Pulse Width in Rising Edge Mode 2 TwINTHR High Level Pulse Width in Rising Edge Mode 3 TwINTHF High Level Pulse Width in Falling Edge Mode 4 TwINTLF Low Level Pulse Width in Falling Edge Mode Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period ...
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... Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. WAKE-UP MANAGEMENT TIMING WKUPn n=0-3 ST92141 - ELECTRICAL CHARACTERISTICS = 50pF 25MHz, unless otherwise specified) Load INTCLK Parameter -V ...
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... ST92141 - ELECTRICAL CHARACTERISTICS RCCU CHARACTERISTICS ( 10 40°C to +85°C, C – Symbol Parameter V RESET Input High Level IHRS V RESET Input Low Level ILRS V RESET Input Hysteresis HYRS I RESET Pin Input Leakage LKRS Note: (1) Unless otherwise stated, typical data are based on T duction ...
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... OSCIN/OSCOUT Pins Input I LKOS Leakage T Oscillator Start-up Time STUP Note: (1) Unless otherwise stated, typical data are based on T duction. (2) Typical value with OSCIN=5MHz, CL=33pF on OSCIN-OSCOUT, T ST92141 - ELECTRICAL CHARACTERISTICS = 50pF 25MHz, unless otherwise specified) Load INTCLK Comment Min Fundamental mode 3 crystal only 0.6 External Clock 0 ...
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... ST92141 - ELECTRICAL CHARACTERISTICS WATCHDOG TIMING TABLE ( 10 40°C to +85°C, C – unless otherwise specified) N° Symbol Parameter 1 TwWDOL WDOUT Low Pulse Width 2 TwWDOH WDOUT High Pulse Width 3 TwWDIL WDIN High Pulse Width 4 TwWDIH WDIN Low Pulse Width Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, watchdog prescaler and counter programmed values ...
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... Psc = Standard Timer Prescaler Register content (STP): from 0 to 255 Cnt = Standard Timer Counter Registers content (STH,STL): from 0 to 65535 T = Standard Timer Input signal period (STIN). STIN STANDARD TIMER TIMING ST92141 - ELECTRICAL CHARACTERISTICS = 50pF 25MHz, Push-pull output configuration, Load INTCLK Value (Note) ...
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... ST92141 - ELECTRICAL CHARACTERISTICS EXTENDED FUNCTION TIMER EXTERNAL TIMING TABLE ( 10 40°C to +105°C, C – N° Symbol 1 Tw External Clock low pulse width (EXTCLK) PEWL 2 Tw External Clock high pulse width (EXTCLK) PEWH 3 Tw Input Capture low pulse width (ICAPx) ...
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... Measurement points are taken with reference to V (1) Values guaranteed by design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. ST92141 - ELECTRICAL CHARACTERISTICS = 50pF, f Load INTCLK Condition Master ...
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... ST92141 - ELECTRICAL CHARACTERISTICS SPI Master Timing Diagram CPHA=0, CPOL=0 SS (INPUT) SCK (OUTPUT) MISO (INPUT) 6 MOSI (OUTPUT) 10 SPI Master Timing Diagram CPHA=0, CPOL=1 SS (INPUT) SCK (OUTPUT) MISO (INPUT) 6 MOSI (OUTPUT) 10 SPI Master Timing Diagram CPHA=1, CPOL=0 SS (INPUT) SCK (OUTPUT) 4 MISO (INPUT) 6 MOSI ...
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... SPI Slave Timing Diagram CPHA=1, CPOL=0 SS (INPUT) 2 SCK (INPUT) 4 HIGH-Z MISO (OUTPUT) 8 MOSI (INPUT) 6 SPI Slave Timing Diagram CPHA=1, CPOL=1 SS (INPUT) 2 SCK (INPUT) 5 HIGH-Z MISO (OUTPUT) 8 MOSI (INPUT) 6 ST92141 - ELECTRICAL CHARACTERISTICS D6-OUT 10 11 D6- D6-OUT 10 11 D6- D7-OUT D6-OUT 10 D7-IN D6- ...
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... ST92141 - ELECTRICAL CHARACTERISTICS A/D EXTERNAL TRIGGER TIMING TABLE ( 10 40°C to +85°C, C – N° Symbol Parameter 1 Tw External trigger pulse width LOW 2 Tw External trigger pulse distance HIGH 3 Tw External trigger active edges distance EXT 4 Td EXTRG falling edge and first conversion start ...
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... Simulated value. (6) The specified values are guaranteed only if an overload condition occurs on a maximum of 2 non-selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. ST92141 - ELECTRICAL CHARACTERISTICS = 25MHz, unless otherwise specified) Typical ...
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... ST92141 - ELECTRICAL CHARACTERISTICS Figure 81. A/D Conversion Characteristics 255 254 253 252 251 250 code out LSB (ideal Offset Error OSE 172/179 1 Offset Error OSE ( (5) (1) Example of an actual transfer curve (2) The ideal transfer curve ...
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... Tck = INTCLK period = OSCIN period when OSCIN is not divided OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. IMC TIMING TACHO NMI 5 / NMI UH/UL/VH/VL/WH/WL ST92141 - ELECTRICAL CHARACTERISTICS = 50pF 25MHz, unless otherwise specified) Load INTCLK Parameter -V for positive pulse and V -V for negative pulse ...
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... ST92141 - GENERAL INFORMATION 9 GENERAL INFORMATION 9.1 PACKAGE MECHANICAL DATA 32-PIN SHRINK PLASTIC DUAL IN LINE PACKAGE See Lead Detail 34-PIN PLASTIC SMALL OUTLINE PACKAGE 0.10mm .004 seating plane 174/179 VR01725J N/2 SO34S mm inches Dim ...
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... SHRINK CERAMIC DUAL IN-LINE PACKAGE ST92141 - GENERAL INFORMATION Dim. Min A A1 0.38 B 0.36 0.46 0.58 0.014 0.018 0.023 B1 0.64 0.89 1.14 0.025 0.035 0.045 C 0.20 0.25 0.36 0.008 0.010 0.014 D 29.41 29.97 30.53 1.158 1.180 1.202 D1 26.67 E 10.16 E1 9.45 9.91 10.36 0.372 0.390 0.408 14. Ø CDIP32SW N mm inches Typ Max Min Typ Max 3.63 0.143 0.015 1 ...
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... ST92141 - GENERAL INFORMATION 9.2 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics. 9.3 Transfer of Customer Code Customer code is made up of the FASTROM ( Factory Advanced Service Technique ROM) con- tents. The FASTROM contents are to be sent on diskette electronic means, with the hexadec- Figure 82 ...
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... We have checked the FASTROM code verification file returned STMicroelectronics. It con- forms exactly with the FASTROM code file orginally supplied. We therefore authorize STMicroelec- tronics to proceed with device manufacture. Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST92141 - GENERAL INFORMATION STMicroelectronics OPTION LIST [ ] ST92P141K4B6/xxx ST92P141K4M6/xxx Tube [ ] Tape & Reel (not available for SDIP packages STMicroelectronics ...
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... ST92141 - SUMMARY OF CHANGES 10 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Rev. Added paragraph in section “PLL Clock Multiplier Programming” on page 66 about mandatory use of the divide-by-two prescaler for PLL operation. 1.7 Updated Option List ...
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... C system is granted provided that the system conforms to the I Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. ST92141 - SUMMARY OF CHANGES 2001 STMicroelectronics - All Rights Reserved Standard Specification as defined by Philips. ...