ST62T42B ST Microelectronics, ST62T42B Datasheet
ST62T42B
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ST62T42B Summary of contents
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... ST6242-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port). DEVICE SUMMARY OTP EPROM DEVICE (Bytes) (Bytes) ST62T42B 7948 - ST62E42B 7948 August 1999 ST62T42B/E42B EEPROM AND A/D CONVERTER with 7-bit (See end of Datasheet for Ordering Information) I/O Pins PQFP64 CQFP64W Rev. 2.6 1/68 1 ...
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... ST62T42B/E42B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.5 Data Window Register (DWR 1.3.6 Data RAM/EEPROM Bank Register (DRBR 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 ...
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ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST6242B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... EPROM/OTP versions only) PP common core is surrounded by a number of on- chip peripherals. The ST62E42B is the erasable EPROM version of the ST62T42B device, which may be used to em- ulate the ST62T42B device, as well as the respec- tive ST6242B ROM devices. PORT A 8-BIT PORT B PORT C LCD DRIVER ...
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... ST62T42B/E42B INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/EPROM versions.OTP devices offer all the advantages of user programmability at low cost, ...
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... S33..S40 are alternate functions of the Port C I/O pins. (Combiports feature) VLCD. Display voltage supply. It determines the high voltage level on COM1-COM4 and S4-S48 pins. VLCD1/3, VLCD2/3. Display supply voltage inputs for determining the display voltage levels on COM1-COM4 and S4-S48 pins during multiplex operation. ST62T42B/E42B 7/68 7 ...
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... ST62T42B/E42B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code in Program memory and user vectors; Data space contains user data in RAM and in Program ...
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... EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the Program memory contents. Returned parts with a protection set can therefore not be accepted. ST62T42B/E42B PRPR1 PRPR0 PC bit 11 Memory Page ...
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... Program memory. 1.3.3.2 Data RAM/EEPROM In ST62T42B and ST62E42B devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the pe- ...
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... DWR is not affected ST62T42B/E42B 0 0 PROGRAM SPACE ADDRESS READ 0 DATA SPACE ADDRESS 40h-7Fh IN INSTRUCTION DATA SPACE ADDRESS 1 59h 1 VR01573A 11/68 11 ...
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... DRBR is not affected. In DRBR Register, only 1 bit must be set. Other- wise two or more pages are enabled in parallel, producing errors. Table 6. Data RAM Bank Register Set-up DRBR 00h 01h 02h 08h 10h1 other ST62T42B/E42B None EEPROM Page 0 EEPROM Page 1 RAM Page 1 RAM Page 2 Reserved ...
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... EECTL it must also write to the image register. The image register must be written to first so that interrupt oc- curs between the two instructions, the EECTL will not be affected ST62T42B/E42B Dataspace addresses. Banks 0 and 38h-3Fh 30h-37h 28h-2Fh ...
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... ST62T42B/E42B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle resetting E2PAR2 without programming the EEPROM ...
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... PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V programming flow of the ST62T42B/E42B is de- scribed in the User Manual of the EPROM Pro- gramming Board. The MCUs can be programmed with the ST62E4xB EPROM programming tools available from STMicroelectronics ...
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... ST62T42B/E42B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally ...
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... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is ST62T42B/E42B automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hard- ware stack which eliminates the need for a stack pointer ...
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... ST62T42B/E42B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 Main Oscillator The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator. Figure 8 illustrates various possible oscillator con- figurations using an external crystal or ceramic res- onator, an external clock input ...
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... RESET pin. Figure 10. Reset and Interrupt Processing has DD RESET NMI MASK SET INT LATCH CLEARED ( IF PRESENT ) SELECT NMI MODE FLAGS PUT FFEH ON ADDRESS BUS YES IS RESET STILL PRESENT? LOAD PC FROM RESET LOCATIONS FFE/FFF FETCH INSTRUCTION ST62T42B/E42B supply DD NO VA000427 19/68 19 ...
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... ST62T42B/E42B RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst oth- er things, resets the watchdog counter. ...
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... EEPROM enabled I/O are Input with pull-up 00h Interrupt disabled SPI disabled LCD display off Interrupt disabled FFh LCD Output Undefined As written if programmed 00h FFh TIMER 1 disabled/Max count loaded 7Fh 00h FFh TIMER 2 disabled/Max count loaded 7Fh FEh 40h A/D in Standby ST62T42B/E42B Comment 21/68 21 ...
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... ST62T42B/E42B 3.3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly ...
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... Reset when it changes to “0”. This offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8MHz, this is equivalent to timer peri- ods ranging from 384 s to 24.576ms). ST62T42B/E42B Figure 13. Watchdog Counter Control ...
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... ST62T42B/E42B DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110b Bit Watchdog Control bit If the hardware option is selected, this bit is forced high and the user cannot change it (the Watchdog is always active). When the software option is se- ...
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... Reset (hardware activation). It should be noted that when the GEN bit is low (in- terrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes SET DB 1.7 LOAD SET 8 WRITE RESET DATA BUS ST62T42B/E42B -12 OSCILLATOR CLOCK VA00010 25/68 25 ...
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... ST62T42B/E42B 3.4 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated interrupt service routine. These vectors are located in Pro- gram space (see Table 10) ...
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... The interrupt is serviced. – Return from interrupt (RETI) ST62T42B/E42B MCU – Automatically the MCU switches back to the nor- mal flag set (or the interrupt flag set) and pops the previous PC value from the stack. ...
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... ST62T42B/E42B INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations. Address: 0C8h — Write Only ...
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... Start CLK Q CLR MUX I Start 1 1 IOR bit 6 (LES) FF CLK Q CLR I Start 2 IOR bit 5 (ESB) TMZ ETI TMZ ETI EAI EOC IOR bit 4(GEN) ST62T42B/E42B INT #0 NMI (FFC,D)) INT #1 (FF6,7) RESTART FROM STOP/WAIT INT #2 (FF4,5) INT #3 (FF2,3) INT #4 (FF0,1) VR0426S 29/68 29 ...
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... ST62T42B/E42B 3.5 POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following paragraphs. 3.5.1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed. The microcontroller can be considered as being in a “ ...
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... Nevertheless, two cases must be consid- ered: – If the interrupt is a normal one, the interrupt rou- tine in which the WAIT or STOP mode was en- ST62T42B/E42B tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode ...
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... ST62T42B/E42B 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with pull-up, but without interrupt – Analog input – Push-pull output – ...
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... Mode Input With pull-up, no interrupt Input No pull-up, no interrupt Input With pull-up and with interrupt Input Analog input (when available) Output Open-drain output (20mA sink when available) Output Push-pull output (20mA sink when available) ST62T42B/E42B Optio n 33/68 33 ...
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... Output Open Drain Output Push-pull Note *. xxx = DDR, OR, DR Bits respectively Table 14. I/O Port configuration for the ST62T42B/E42B Note 1. Provided the correct configuration has been selected. 34/68 34 outputs advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole ...
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... PA4-PA7 Analog Input PB2-PB3 Open drain output PA4-PA7 5mA PB2-PB7 PC0-PC7 (1mA) Open drain output PB4-PB7 20mA Push-pull output PA4-PA7 5mA PB2-PB7 PC0-PC7 (1mA) Push-pull output PB4-PB7 20mA (1) SCHEMATIC ADC ST62T42B/E42B Data in Interrupt Data in Interrupt Data in Interrupt Data out Data out 35/68 35 ...
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... ST62T42B/E42B I/O PORTS (Cont’d) 5.0.1 LCD alternate functions (combiports) PC0 to PC7 can also be individually defined as 8 LCD segment output by setting DDRC, ORC and DRC registers as shown in Table 15. On the contrary with other I/O lines, the reset state is the LCD output mode. These 8 segment lines are recognised as S33 ...
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... Px3 Px2 Bit 7-0 = Px7 - Px0: Port Data Direction Registers bits. 5.0.5 I/O Port Data Registers DRA/B/C (C0h PA, C1h PB, C3h PC) Read/Write 0 7 Px7 Px6 Px5 Px1 Px0 Bit 7-0 = Px7 - Px0: Port Data Registers bits. 0 Px1 Px0 ST62T42B/E42B 0 Px4 Px3 Px2 Px1 Px0 37/68 37 ...
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... ST62T42B/E42B 5.1 TIMER 1 & 2 The MCU features two on-chip Timer peripheral named TIMER 1 & TIMER 2. Each of these timers consist of an 8-bit counter with a 7-bit programma- ble prescaler, giving a maximum count of 2 The content of the 8-bit counter can be read/writ- ten in the Timer/Counter register, TCR, while the state of the 7-bit prescaler can be read in the PSC register ...
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... Figure 21. TIMER 1 & 2 Block Diagram PSC INT DATA BUS 8 8-BIT COUNTER STATUS/CONTROL SELECT REGISTER TMZ ETI D5 3 ST62T42B/E42B PSI PS2 PS1 PS0 INTERRUPT LINE VR02070A 39/68 39 ...
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... ST62T42B/E42B TIMER 1& 2 (Cont’d) 5.1.1 TIMER 1 & 2 Operating Mode The Timer prescaler is clocked by the prescaler clock input (f 12). INT The user can select for each TIMER the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR ...
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... Timer Counter Register (TCR) Address: 0D3h — Read/Write Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D2h — Read/Write Bit 7 = D7: Always read as ”0”. Bit 6-0 = D6-D0: Prescaler Bits. ST62T42B/E42B PS0 Divided ...
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... ST62T42B/E42B TIMER 1& 2 (Cont’d) 5.1.5 TIMER 2 Registers Timer Status Control Register (TSCR) Address: 0D7h — Read/Write 7 TMZ ETI D5 D4 PSI PS2 Bit 7 = TMZ: Timer Zero bit A low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before starting a new count ...
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... If PDS=“1”, the A/D is powered and en- abled for conversion. This bit must be set at least one instruction before the beginning of the conver- ST62T42B/E42B sion to allow stabilisation of the A/D converter. This action is also needed before entering WAIT mode, since the A/D comparator is not automati- cally disabled in WAIT mode ...
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... ST62T42B/E42B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ply voltages used as analog references. The accuracy of the conversion depends on the ...
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... SPI Interrupt Disable Register Write SPI Data Register Read RESET Q4 RESET 4-Bit Counter CP Q4 (Q4=High after Clock8) Reset 8-Bit Data Load CP Shift Register DOUT DIN Output 8-Bit Tristate Data I/O Enable DOUT D0..... ......... ......... .....D7 to Processor Data Bus ST62T42B/E42B Set Res Interrupt VR01504 45/68 45 ...
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... ST62T42B/E42B SERIAL PERIPHERAL INTERFACE (Cont’d) After 8 clock pulses (D7..D0) the output Q4 of the 4-bit binary counter becomes low, disabling the clock from the counter and the data/shift register. Q4 enables the clock to generate an interrupt on the 8th clock falling edge as long as no reset of the counter (processor write into the 8-bit data/shift register) takes place ...
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... It is not recommended to select an internal frequency lower than 32.768KHz as the clock su- pervisor circuit may switch off the LCD peripheral if lower frequency is detected. BACKPLA NES COMMON DRIVE R CONTROLLER 32KHz CONTROL REGISTE R DATA BUS ST62T42B/E42B Division Factor 0 Clock disabled: Display off 128 0 256 ...
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... ST62T42B/E42B LCD CONTROLLER-DRIVER (Continued) 5.4.1 Multiplexing ratio and frame frequency setting common plates COM1..COM4 can be used for multiplexing ratio ranging from 1/1 to 1/4. The selection is made by the bits DS0 and DS1 of the LCDCR as shown in the Table 19. Table 19. Multiplexing ratio DS1 DS0 Display Mode ...
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... S11 S10 S22 S21 S20 S19 S18 S30 S29 S28 S27 S26 S38 S37 S36 S35 S34 S46 S45 S44 S43 S42 ST62T42B/E42B LCD if the V con- LCD LCD LSB NA S9 S17 COM1 S25 S33 S41 NA S9 S17 COM2 S25 S33 S41 NA ...
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... ST62T42B/E42B LCD CONTROLLER-DRIVER (Continued) 5.4.4 Stand by or STOP operation mode No clock from the main oscillator is available in STOP mode for the LCD controller, and the con- troller is switched off when the STOP instruction is executed. All segment and common lines are then switched to ground to avoid any DC biasing of the LCD elements ...
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... Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant ST62T42B/E42B bits of the opcode with the byte following the op- code. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space ...
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... ST62T42B/E42B 6.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following par- agraphs describe the different types ...
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... Cycles ST62T42B/E42B Flags 53/68 53 ...
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... ST62T42B/E42B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations ...
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... Indicates Ill egal Instructions Cycle 5 Bit Displacement Operand 3 Bit Address 1byte dataspace address Bytes 1 byte immediate data 12 bit address Addressing Mode 8 bit Displacement ST62T42B/E42B LOW 6 7 0110 0111 HI 2 JRC a,(x) 0000 1 prc 1 ind JRC 4 LDI ...
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... ST62T42B/E42B Opcode Map Summary (Continued) LOW 8 9 1000 1001 1010 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 JRNZ abc 0010 1 pcr 2 ext 1 2 JRNZ abc 0011 1 pcr 2 ...
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... RthJA = Package thermal resistance . DD (junction-to ambient Pint + Pport. DD Pint = IDD x VDD (chip internal power). Pport = Port power dissipation (deter- mined by the user). Parameter (source) (sink) SS ST62T42B/E42B Ambient Temperature. Value Unit -0.3 to 7.0 V ( ( ...
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... ST62T42B/E42B 7.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the A/D conversion ...
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... Pull-Up configured RESET SS f =8MHz OSC V =5.0V f =8MHz DD INT V =5.0V f =8MHz DD INT I =0mA LOAD V =5.0V DD ST62T42B/E42B Value Unit Min. Typ. Max 0 0.7 V 0.2 V 0.2 0.1 0.8 V 0.1 0.8 1.3 4.9 V 3.5 40 100 200 150 350 900 0.1 1 -16 - ...
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... ST62T42B/E42B 7.4 AC ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter (1) t Supply Recovery Time REC Minimum Pulse Width ( RESET pin WR NMI pin T EEPROM Write Time WEE Endurance EEPROM WRITE/ERASE Cycle Retention EEPROM Data Retention C Input Capacitance IN C Output Capacitance OUT Notes: 1 ...
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... LCD 4.5 I= =5V LCD I=100 A, V =5V LCD I= =5V LCD See Note 2 V -0.2 DD Value Test Conditio ns Min. Typ. Vss V =5.0V PSS A PSS Running PSS Stopped ST62T42B/E42B Unit Max. f INT --------- - MHz Unit Max. 1 MHz ns ns Unit Max 0.5 10 Unit Max ...
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... ST62T42B/E42B 8 GENERAL INFORMATION 8.1 PACKAGE MECHANICAL DATA Figure 30. 64-Pin Plastic Quad Flat Package Figure 31. 64-Pin Ceramic Quad Flat Package 62/68 62 Dim Min A A1 0.25 A2 2.55 2.80 3.05 0.100 0.110 0.120 B 0.30 C 0.13 D 16.95 17.20 17.45 0.667 0.677 0.687 D1 13.90 14.00 14.10 0.547 0.551 0.555 D3 E 16.95 17.20 17.45 0.667 0.677 0.687 E1 13.90 14.00 14.10 0.547 0.551 0.555 0.65 0.80 0.95 0.026 0.031 0.037 ...
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... Thermal Resistance 8.3 ORDERING INFORMATION Table 28. OTP/EPROM VERSION ORDERING INFORMATION Program Sales Type Memory (Bytes) ST62E42BG1 7948 (EPROM) ST62T42BQ6 7948 (OTP) Value Test Conditions Min. Typ. PQFP64 CQFP64W I/O Temperature Range to18 - ST62T42B/E42B Unit Max. 70 C/W 70 Package CQFP64W PQFP64 63/68 63 ...
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... ST62T42B/E42B Notes: 64/68 64 ...
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Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +85 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size ...
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... ST6242B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6242B is mask programmed ROM version of ST62T42B OTP devices. It offers the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form 0.5s min TEST 15 14V typ 10 5 TEST ...
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ST6242B MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . . . . ...
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ST6242B 1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options. ...