ST92141 STMicroelectronics, ST92141 Datasheet - Page 41

• Manufacturer Part Number: ST92141
• Description: 8/16-bit Mcu For 3-phase Ac Motor Control
• Manufacturer: STMicroelectronics

PRIORITY LEVEL ARBITRATION (Cont’d)
with the highest position in the chain, as shown in
Table
Table 11. Daisy Chain Priority
3.4.4 Dynamic Priority Level Modification
The main program and routines can be specifically
prioritized. Since the CPL is represented by 3 bits
in a read/write register, it is possible to modify dy-
namically the current priority value during program
execution. This means that a critical section can
have a higher priority with respect to other inter-
rupt requests. Furthermore it is possible to priori-
tize even the Main Program execution by modify-
ing the CPL during its execution. See
Figure 16. Example of Dynamic priority
level modification in Nested Mode
3.5 ARBITRATION MODES
The ST9 provides two interrupt arbitration modes:
Concurrent mode and Nested mode. Concurrent
mode is the standard interrupt arbitration mode.
Nested mode improves the effective interrupt re-
sponse time when service routine nesting is re-
quired, depending on the request priority levels.
Highest Position
Lowest Position
6
4
5
7
Priority Level
CPL is set to 5
11.
ei
INTERRUPT 6 HAS PRIORITY LEVEL 6
MAIN
INT6
CPL6 > CPL5:
INT6 pending
INTA0 / Watchdog Timer
INTA1 / Standard Timer
INTB0 / Extended Function Timer
INTC1 / SPI
INTD0 / RCCU
INTD1 / WKUP MGT
Induction Motor Controller
AD Converter
CPL is set to 7
by MAIN program
CPL=6
INT 6
Figure 16
CPL=7
MAIN
The IAM control bit in the CICR Register selects
Concurrent Arbitration mode or Nested Arbitration
Mode.
3.5.1 Concurrent Mode
This mode is selected when the IAM bit is cleared
(reset condition). The arbitration phase, performed
during every instruction, selects the request with
the highest priority level. The CPL value is not
modified in this mode.
Start of Interrupt Routine
The interrupt cycle performs the following steps:
– All maskable interrupt requests are disabled by
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
– If ENCSR is set, CSR is loaded with ISR con-
End of Interrupt Routine
The Interrupt Service Routine must be ended with
the iret instruction. The iret instruction exe-
cutes the following operations:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
– If ENCSR is reset, CSR is used instead of ISR.
Normal program execution thus resumes at the in-
terrupted instruction. All pending interrupts remain
pending until the next ei instruction (even if it is
executed during the interrupt service routine).
Note: In Concurrent mode, the source priority level
is only useful during the arbitration phase, where it
is compared with all other priority levels and with
the CPL. No trace is kept of its value during the
ISR. If other requests are issued during the inter-
rupt service routine, once the global CICR.IEN is
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
clearing CICR.IEN.
stack.
the Vector Table, pointed to by the IVR.
tents; otherwise ISR is used in place of CSR until
iret instruction.
stack.
the CICR.IEN bit.
ST92141 - INTERRUPTS
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