ST92196A STMicroelectronics, ST92196A Datasheet - Page 194

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
8.11.3.1 Data transfer
Data to be transmitted by the SCI is first loaded by
the program into the Transmitter Buffer Register.
The SCI will transfer the data into the Transmitter
Shift Register when the Shift Register becomes
available (empty). The Transmitter Shift Register
converts the parallel data into serial format for
transmission via the SCI Alternate Function out-
put, Serial Data Out. On completion of the transfer,
the transmitter buffer register interrupt pending bit
will be updated. If the selected word length is less
than 8 bits, the unused most significant bits do not
need to be defined.
Incoming serial data from the Serial Data Input pin
is converted into parallel format by the Receiver
Shift Register. At the end of the input data frame,
the valid data portion of the received word is trans-
ferred from the Receiver Shift Register into the Re-
ceiver Buffer Register. All Receiver interrupt con-
ditions are updated at the time of transfer. If the
selected character format is less than 8 bits, the
unused most significant bits will be set.
The Frame Control and Status block creates and
checks the character configuration (Data length
and number of Stop bits), as well as the source of
the transmitter/receiver clock.
The internal Baud Rate Generator contains a pro-
grammable divide by “N” counter which can be
used to generate the clocks for the transmitter
and/or receiver. The baud rate generator uses
INTCLK as the clock source.
The Address bit/D9 is optional and may be added
to any word. It is commonly used in network or ma-
chine control applications. When enabled (AB set),
an address or ninth data bit can be added to a
transmitted word by setting the Set Address bit
(SA). This is then appended to the next word en-
tered into the (empty) Transmitter Buffer Register
and then cleared by hardware. On character input,
a set Address Bit can indicate that the data pre-
ceding the bit is an address which may be com-
pared in hardware with the value in the Address
Compare Register (ACR) to generate an Address
Match interrupt when equal.
The Address bit and Address Comparison Regis-
ter can also be combined to generate four different
types of Address Interrupt to suit different proto-
cols, based on the status of the Address Mode En-
able bit (AMEN) and the Address Mode bit (AM) in
the CHCR register.
- SERIAL COMMUNICATIONS INTERFACE (SCI)
The character match Address Interrupt mode may
be used as a powerful character search mode,
generating an interrupt on reception of a predeter-
mined character e.g. Carriage Return or End of
Block codes (Character Match Interrupt).
The Line Break condition is fully supported for both
transmission and reception. Line Break is sent by
setting the SB bit (IDPR). This causes the trans-
mitter output to be held low (after all buffered data
has been transmitted) for a minimum of one com-
plete word length and until the SB bit is Reset.
Testing of the communications channel may be
performed using the built-in facilities of the SCI pe-
ripheral. Auto-Echo mode and Loop-Back mode
may be used individually or together.
Table 40. Address Interrupt Modes
Figure 86. Auto Echo Configuration
Figure 87. Loop Back Configuration
Figure
Configuration
If 9th Data Bit is set
If Character Match
If Character Match and 9th Data Bit is set
If Character Match Immediately Follows BREAK
TRANSMITTER
TRANSMITTER
TRANSMITTER
RECEIVER
RECEIVER
RECEIVER
88.
Auto
Echo
LOGICAL 1
and
Loop-Back
SOUT
SIN
SOUT
SIN
SOUT
SIN
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