ST92196A STMicroelectronics, ST92196A Datasheet - Page 163

• Manufacturer Part Number: ST92196A
• Description: 8/16-bit Mcu For Tv Applications With Up To 96k Rom, On-screen-display And 1 Or 2 Data Slicers
• Manufacturer: STMicroelectronics

DATA SLICER (Cont’d)
8.6.4 Interrupt handling
If the device has two data slicers, both use the
same interrupt channel. So some additional soft-
ware is needed, when using both slicers at the
same time. Using only one of them (i.e. DS0) al-
lows for software compatibility with the ST9296.
The interrupt requests, issued by the two slicers
are ORed in order to generate an interrupt signal
on the same ST9 interrupt channel.
The internal signals IRQ1 for DS0 / IRQ2 for DS1
(see
number matches the value set by the user in the
first control register and this signal is reset at the
end of the line: the IRQ_INV bit in the CR1 register
allows to select whether the rising edge or the fall-
ing edge of this signal will cause a positive pulse
on CCIRQ1 or CCIRQ2. As the CCIRQ pulses are
very short, the TED0 control bit in the EITR regis-
ter is of very limited use. It is recommended to
keep this bit always at “1” (interrupt on rising
edge).
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- CLOSED CAPTION DATA SLICER (DS)
Figure
68) are activated when the line
In order to find out the source of an interrupt re-
quest, each of the two slicers sets the IRFL bit in
the CR2 register when an interrupt request is is-
sued. Both of these flags (IRFL for DS0 and DS1)
must be scanned and then cleared by the software
during every interrupt service routine.
Note: There are situations where data has to be
recovered from one or more lines in only one field,
i.e. either Field#1 or Field#2. In such cases an un-
necessary interrupt is generated in the field that
does not contain any lines with data that is of inter-
est. For example, to recover closed caption data
on Line#21 in Field#1, the half line count LN[5:0] in
the CR1 regsiter can be permanently set to 33.
This value of LN[5:0] will also cause an interrupt to
be generated in the middle of Line#21 in Field#2.
The interrupt routine must therefore determine the
status of the FIELD1 bit in the MR register and im-
mediately return to the main program if this bit is
low.
Note: An interrupt is always generated at the end
of the specified line (and on the corresponding line
of the opposite field).