ST92196A STMicroelectronics, ST92196A Datasheet

Page 1

... Multi-Function timer* Eight 8-bit programmable PWM outputs * On some devices October 2003 . ST92196A ST92T196 ST92E196 NMI and 6 external interrupts data slicers for Closed Captioning and Extended Data Service data extraction independent video sources. Support for FCC V- Chip and Gemstar bitstream decoding ...

Page 2

... ST92196A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.1 Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.2 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4 On-chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.1 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.2 I/O Port Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 REQUIRED EXTERNAL COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5 ST92196A REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 ...

Page 3

... ST92196A 3.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.1 Priority level 7 (Lowest 3.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.9 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.10 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 ON-CHIP DIRECT MEMORY ACCESS (DMA ...

Page 4

... Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.6.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.7 VIDEO SYNC ERROR DETECTOR (SYNCERR 168 8.7.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.7.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.8 IR PREPROCESSOR (IR 169 8.8.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.8.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 2 8.9 FOUR-CHANNEL I C BUS INTERFACE (I2C 170 8.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 8.9.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 8.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ST92196A 4/268 ...

Page 5

... ST92196A 8.9.4 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8.9.5 Error Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8.9.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8.10 SERIAL PERIPHERAL INTERFACE (SPI 182 8.10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.10.2 Device-Specific Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.10.4 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 8.10.5 Working With Other Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.10.6 I2C-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.10.7 S-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8.10.8 IM-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 8.10.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 8 ...

Page 6

... I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 1.2.2 I/O Port Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 1.3 REQUIRED EXTERNAL COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 1.5 ST92E196A/B & ST92T196A/B REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 3 EPROM/OTP PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 4 PACKAGE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 ST92196A 6/268 ...

Page 7

... ST92196A 7/268 ...

Page 8

... Core Architecture The nucleus of the ST92196A is the enhanced ST9 Core that includes the Central Processing Unit (CPU), the register file, the interrupt and DMA controller. Three independent buses are controlled by the ...

Page 9

... GENERAL DESCRIPTION INTRODUCTION (Cont’d) Figure 1. ST92196A Architectural Block Diagram 32 to 96K ROM RAM OSDRAM Controller 384 bytes RAM 256 bytes Register File 8/16 bits CPU INT[7:0] DMA/Interrupt NMI Management ST9+ CORE OSCIN OSCOUT RCCU RESET RESETI WATCHDOG TIMER TINA TINB ...

Page 10

INTRODUCTION (Cont’d) 1.1.4 On-chip Peripherals OSD Controller The On Screen Display displays closed caption or extended service format data received from the on-chip data slicers or any text or menu data gen- erated by the application. Rows ...

Page 11

GENERAL DESCRIPTION 1.2 PIN DESCRIPTION Figure 2. 64-Pin Thin QFP Package Pin-Out N.C. AIN6/P0.6 AIN5/P0.5 AIN4/P0.4 AIN0/P0.3 P0.2 P0.1 P0.0 CCVIDEO1 V DD2 CCVIDEO2*/P3.7 SYNDET0/DSOUT1/P3.6 SDA2/TINA*/P3.5 SCL2/TOUTA*/INT1/P3.4 SYNDET1/DSOUT2*/P3.3 N.C. N.C. = Not connected * Not available on some devices. 11/268 ...

Page 12

PIN DESCRIPTION (Cont’d) Figure 3. 56-Pin Package Pin-Out SCK/SCL1/INT2/P2.4 SDIO/SDA1P2.5 PIXCLK/INT5/P2.7 CCVIDEO2*/P3.7 DSOUT1/SYNDET0/P3.6 TINA*/SDA2/P3.5 INT1/TOUTA*/SCL2/P3.4 DSOUT2/SYNDET1/P3.3 TSLU/SCL3/P3.0 * Not available on some devices. Table 1. Power Supply Pins Name Function V Main Power Supply Voltage DD1 V (2 pins internally ...

Page 13

GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) 1.2.1 I/O Port Configuration All ports can be individually configured as input, bi- directional, output, or alternate function. Refer to the Port Bit Configuration Table in the I/O Port Chapter. No I/O pins have any ...

Page 14

Table 4. I/O Port Alternate Functions Port General Purpose I/O Name SDIP56 TQFP64 P0.0 14 P0.1 13 P0.2 12 P0.3 11 P0.4 10 P0.5 9 P0.6 8 P0.7 7 P2.0 36 P2.1 37 P2.2 38 P2.3 39 All ports useable ...

Page 15

GENERAL DESCRIPTION Port General Purpose I/O Name SDIP56 TQFP64 P3.6 18 P3.7 17 P4.0 43 P4.1 44 All ports useable for general pur- P4.2 45 pose I/O (input, P4.3 46 output or bidi- P4.4 47 rectional) P4.5 48 P4.6 49 ...

Page 16

REQUIRED EXTERNAL COMPONENTS 1µF Slicer 1 input Slicer 2 input (if present or used) 1µF Warning : The decoupling capacitors between analog and digital +5V (V Add a 100NF and a 4.7µF capacitor close to the corresponding pins if ...

Page 17

... GENERAL DESCRIPTION 1.4 MEMORY MAP Figure 4. ST92196A Memory Map 22017Fh 384 bytes OSDRAM 220000h 20FFFFh 1) 4 Kbytes 20FBFFh 1) 3 Kbytes 20F7FFh 1) 2 Kbytes 20F3FFh Internal RAM 1) 1 Kbyte 20F000h 1) 017FFFh 96 Kbytes 128K bytes 1) 00FFFFh 64 Kbytes 1) 00BFFFh 48 Kbytes Internal ROM 1) 32K bytes Note 1: ROM and RAM sizes are product dependent, refer to the Ordering Information section on 234 ...

Page 18

... ST92196A REGISTER MAP Table 6 contains the map of the group F peripheral pages. The common registers used by each peripheral are listed in Table 5. Be very careful to correctly program both: – The set of registers dedicated to a particular function or peripheral. Table 5. Common Registers Function or Peripheral SCI, MFT ...

Page 19

... GENERAL DESCRIPTION ST92196A REGISTER MAP (Cont’d) Table 6. Group F Pages Register Map Resources available on the ST92196A device: Register R255 Res. Res. R254 SPI Port R253 3 Res. R252 WCR Res. R251 Res. R250 WDT Port R249 2 R248 MFT R247 R246 Res ...

Page 20

... ST92196A REGISTER MAP (Cont’d) Table 7. Detailed Register Map Group F Reg. Page Block No. Dec. R224 I/O R226 Port R227 R228 0:5 R229 R230 R231 N/A R232 R233 R234 Core R235 R236 R237 R238 R239 R242 R243 R244 INT R245 R246 R247 0 R248 R249 WDT ...

Page 21

GENERAL DESCRIPTION Group F Reg. Page Block No. Dec. R240 I/O Port R241 4 R242 3 I/O R244 Port R245 5 R246 R240 R241 9 R242 R243 R248 R240 REG0HR R241 R242 REG1HR R243 R244 CMP0HR MFT R245 R246 CMP1HR ...

Page 22

Group F Reg. Register Page Block No. Dec. R240 RDCPR R241 RDAPR R242 TDCPR R243 TDAPR R244 R245 R246 R247 24 SCI0 R248 R248 R249 R250 R251 R252 BRGHR R253 BRGLR R254 R255 R246 OSDBCR2 R247 OSDBCR1 R248 OSDER 42 ...

Page 23

GENERAL DESCRIPTION Group F Reg. Page Block No. Dec. R240 R241 R242 45 DS0 R243 R244 R245 R246 R240 R241 R242 46 DS1 R243 R244 R245 R246 R240 55 RCCU R242 CLK_FLAG R240 R241 R242 R243 R244 R245 PWM R246 ...

Page 24

DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 address- ing ...

Page 25

DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) Figure 6. Register Groups 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS 224 223 Figure 8. Addressing ...

Page 26

MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h and R11100111b represent the ...

Page 27

DEVICE ARCHITECTURE 2.3 SYSTEM REGISTERS The System registers are listed in are used to perform all the important system set- tings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description of ...

Page 28

SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt ...

Page 29

DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. ...

Page 30

SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range ...

Page 31

DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) Figure 9. Pointing to a single group of 16 registers REGISTER BLOCK GROUP NUMBER REGISTER FILE ...

Page 32

SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the ...

Page 33

DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise re- duction when only internal Memory is used. If Port 1 and/or ...

Page 34

SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined 7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) ...

Page 35

DEVICE ARCHITECTURE 2.4 MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address ...

Page 36

MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR ...

Page 37

DEVICE ARCHITECTURE 2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a ...

Page 38

ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ...

Page 39

DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0 Bits 7:0 ...

Page 40

MMU REGISTERS (Cont’d) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has been executed (or ldpp, ...

Page 41

DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) Figure 16. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR 41/268 4M bytes 16K 16K 16K 64K 64K 16K 64K 3FFFFFh 294000h 240000h 23FFFFh 20C000h 200000h 1FFFFFh 040000h 03FFFFh 030000h 020000h 010000h ...

Page 42

MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, ...

Page 43

INTERRUPTS 3 INTERRUPTS 3.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing ...

Page 44

INTERRUPT VECTORING The ST9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically. When an interrupt request is acknowledged, the peripheral interrupt module ...

Page 45

INTERRUPTS 3.2.2 Segment Paging Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compati- bility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, ...

Page 46

Figure 10 Table 10. Daisy Chain Priority Highest Position INTA0 INTA1 INTB0 INTB1 INTC0 INTC1 INTD0 INTD1 SCI Lowest Position MFT 3.4.4 Dynamic Priority Level Modification The main program and ...

Page 47

INTERRUPTS ARBITRATION MODES (Cont’d) Examples In the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. Figure 19. Simple Example of a Sequence of Interrupt ...

Page 48

ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, 20), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher ...

Page 49

INTERRUPTS ARBITRATION MODES (Cont’d) 3.5.2 Nested Mode The difference between Nested mode and Con- current mode, lies in the modification of the Cur- rent Priority Level (CPL) during interrupt process- ing. The arbitration phase is basically identical to Con- current ...

Page 50

ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – The PC high ...

Page 51

INTERRUPTS 3.6 EXTERNAL INTERRUPTS The standard ST9 core contains 8 external inter- rupts sources grouped into four pairs. Table 11. External Interrupt Channel Grouping External Interrupt INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Each source has a trigger control ...

Page 52

EXTERNAL INTERRUPTS (Cont’d) Figure 1. External Interrupts Control Bits and Vectors n Watchdog/Timer End of count TEA0 INT 0 pin TEA1 STIM Timer INT 1 pin SPEN,BMS TEB0 SPI Interrupt INT 2 pin TEB1 I2C Interrupt INT 3 pin DION, ...

Page 53

INTERRUPTS 3.7 TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is ...

Page 54

INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles. If the ...

Page 55

INTERRUPTS 3.10 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit enables the ...

Page 56

INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT TRIGGER REGISTER (EITR) R242 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) 7 TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0 Bit 7 = TED1: INTD1 Trigger Event Bit 6 = TED0: INTD0 ...

Page 57

INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PRIORITY LEVEL REGISTER (EIPLR) R245 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) 7 PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A Bit 7:6 = PL2D, PL1D: INTD0, D1 Priority Level. Bit ...

Page 58

INTERRUPT REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh ENCSR Bit 7, 5:0 = Reserved, keep in reset state. Refer to the external Memory Interface ...

Page 59

ON-CHIP DIRECT MEMORY ACCESS (DMA) 4 ON-CHIP DIRECT MEMORY ACCESS (DMA) 4.1 INTRODUCTION The ST9 includes on-chip Direct Memory Access (DMA) in order to provide high-speed data transfer between peripherals and memory or Register File. Multi-channel DMA is fully supported ...

Page 60

DMA TRANSACTIONS The purpose of an on-chip DMA channel is to transfer a block of data between a peripheral and the Register File, or Memory. Each DMA transfer consists of three operations: – A load from/to the peripheral data ...

Page 61

ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d) When selecting the DMA transaction with memory, bit DCPR.RM (bit 0 of DCPR) must be cleared. To select between using the ISR or the DMASR reg- ister to extend the address, (see ...

Page 62

DMA TRANSACTIONS (Cont’d) 4.4 DMA CYCLE TIME The interrupt and DMA arbitration protocol func- tions completely asynchronously from instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their priority al- lows it. A DMA transfer ...

Page 63

ON-CHIP DIRECT MEMORY ACCESS (DMA) 4.6 DMA REGISTERS As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown here may ...

Page 64

RESET AND CLOCK CONTROL UNIT (RCCU) 5.1 INTRODUCTION The Reset and Clock Control Unit (RCCU) com- prises two distinct sections: – the Clock Control Unit, which generates and manages the internal clock signals. – the Reset/Stop Manager, which detects ...

Page 65

... RESET AND CLOCK CONTROL UNIT (RCCU) 5.3 OSCILLATOR CHARACTERISTICS Because of the real time need of the application assumed the ST92196A will be used with a 4 MHz crystal fed to the Core by the frequency mul- tiplier output after it is started and stabilized. 5.3.1 HALT State When a HALT instruction is processed, it stops the main crystal oscillator preventing any derived clock into the chip ...

Page 66

RESET/STOP MANAGER The RESET/STOP Manager resets the device when one of the three following triggering events occurs: – A hardware reset, consequence of a falling edge on the RESET pin. – A software reset, consequence of an HALT in- ...

Page 67

TIMING AND CLOCK CONTROLLER (TCC) 6 TIMING AND CLOCK CONTROLLER (TCC) 6.1 FREQUENCY MULTIPLIERS Two on-chip frequency multipliers generate the proper frequencies for: the Core/Real time Periph- erals and the Display related time base. They follow the same basic scheme ...

Page 68

FREQUENCY MULTIPLIERS (Cont’d) Off-chip filter components (to be confirmed) – Core frequency multiplier (FCPU pin) : 1.2K ohms plus 100 pF between the FCPU pin and GND. – Skew frequency multiplier (FOSD pin) : 1.2K ohms ...

Page 69

TIMING AND CLOCK CONTROLLER (TCC) 6.2 REGISTER DESCRIPTION SKEW CLOCK CONTROL REGISTER (SKCCR) R254 - Read/ Write Register Page: 43 Reset value: 0000 0000 (00h SKWEN SKDIV2 0 0 SKW3 SKW2 SKW1 SKW0 The HALT ...

Page 70

I/O PORTS 7.1 INTRODUCTION ST9 devices feature flexible individually program- mable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin alloca- tions. These lines, which are logically grouped as 8-bit ports, can be individually programmed to ...

Page 71

I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 ...

Page 72

INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 34. Control Bits Bit 7 PxC2 PxC27 PxC1 PxC17 PxC0 PxC07 n Table 16. Port Bit Configuration Table ( 1... port number) PXC2n 0 PXC1n 0 PXC0n 0 PXn Configuration ...

Page 73

I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 35. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 36. Input Configuration I/O ...

Page 74

INPUT/OUTPUT BIT CONFIGURATION (Cont’d) When Px.n is programmed as an Output: (Figure 37) – The Output Buffer is turned Open-drain or Push-pull configuration. – The data stored in the Output Master Latch is copied both into the ...

Page 75

ALTERNATE FUNCTION ARCHITECTURE 7.5 ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 7.5.1 Pin Declared as I/O A pin ...

Page 76

ON-CHIP PERIPHERALS 8.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip- tion of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be connected to exter- nal ...

Page 77

TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 8.1.2 Functional Description 8.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to section 8.1.3.1 on page 78. The WDIN Input pin can be used in one of ...

Page 78

TIMER/WATCHDOG (Cont’d) 8.1.2.7 Gated Input Mode This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input ...

Page 79

TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 8.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the constant ...

Page 80

TIMER/WATCHDOG (Cont’d) 8.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS (EIVR.2, Top Level Input ...

Page 81

TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 8.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control ...

Page 82

TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable . This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by software. 0: ...

Page 83

STANDARD TIMER (STIM) 8.2 STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip- tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals de- scribed may not be connected to ...

Page 84

STANDARD TIMER (Cont’d) 8.2.2 Functional Description 8.2.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the ...

Page 85

STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 8.2.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled and ...

Page 86

STANDARD TIMER (Cont’d) 8.2.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) 7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8 Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE ...

Page 87

MULTIFUNCTION TIMER (MFT) 8.3 MULTIFUNCTION TIMER (MFT) 8.3.1 Introduction The Multifunction Timer (MFT) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic PWM generation and frequency measurement. The MFT comprises a 16-bit Up/Down counter driven ...

Page 88

MULTIFUNCTION TIMER (Cont’d) The configuration of each input is programmed in the Input Control Register. Each of the two output pins can be driven from any of three possible sources: – Compare Register 0 logic – Compare Register 1 logic ...

Page 89

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 8.3.2 Functional Description The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR). 8.3.2.1 Trigger Events A trigger event may be generated by ...

Page 90

MULTIFUNCTION TIMER (Cont’d) 8.3.2.8 Free Running Mode The timer counts continuously ( Down mode) and the counter value simply overflows or underflows through FFFFh or zero; there is no End Of Count condition as such, and no reloading ...

Page 91

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Every software or external trigger event on REG0R performs a reload from REG0R resetting the Biload cycle. In One Shot mode (reload initiat software external trigger), reloading is ...

Page 92

MULTIFUNCTION TIMER (Cont’d) 8.3.3 Input Pin Assignment The two external inputs (TxINA and TxINB) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and falling edges) by ...

Page 93

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 8.3.3.1 TxINA = I/O - TxINB = I/O Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be made ...

Page 94

MULTIFUNCTION TIMER (Cont’d) 8.3.3.9 TxINA = Clock Up - TxINB = Clock Down The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the up/down control are ...

Page 95

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 8.3.3.13 Autodiscrimination Mode The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and the ...

Page 96

MULTIFUNCTION TIMER (Cont’d) 8.3.4 Output Pin Assignment Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register (OBCR) define the driver for ...

Page 97

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to “0”. ...

Page 98

MULTIFUNCTION TIMER (Cont’d) 8.3.5 Interrupt and DMA 8.3.5.1 Timer Interrupt The timer has 5 different Interrupt sources, be- longing to 3 independent groups, which are as- signed to the following Interrupt vectors: Table 20. Timer Interrupt Structure Interrupt Source Vector ...

Page 99

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Figure 49. Pointer Mapping for Register to Register Transfers Register File 8 bit Counter XXXXXX11 8 bit Addr Pointer XXXXXX10 8 bit Counter XXXXXX01 8 bit Addr Pointer XXXXXX00 8.3.5.4 DMA Transaction Priorities ...

Page 100

MULTIFUNCTION TIMER (Cont’d) 8.3.5.6 DMA End Of Block Interrupt Routine An interrupt request is generated after each block transfer (EOB) and its priority is the same as that assigned in the usual interrupt request, for the two channels ...

Page 101

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) CAPTURE LOAD 0 HIGH REGISTER (REG0HR) R240 - Read/Write Register Page: 10 Reset value: undefined 7 R15 R14 R13 R12 R11 This register is used to capture values from the Up/Down counter or ...

Page 102

MULTIFUNCTION TIMER (Cont’d) TIMER CONTROL REGISTER (TCR) R248 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CCP CCMP CEN CCL UDC 0 0 Bit 7 = CEN: Counter enable . This bit is ANDed with the Global ...

Page 103

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) TIMER MODE REGISTER (TMR) R249 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 OE1 OE0 BM RM1 RM0 ECK REN Bit 7 = OE1: Output 1 enable. 0: Disable the ...

Page 104

MULTIFUNCTION TIMER (Cont’d) EXTERNAL INPUT CONTROL (T_ICR) R250 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 IN3 IN2 IN1 IN0 A0 Bits 7:4 = IN[3:0]: Input pin function. These bits are set and cleared by software. TxINA ...

Page 105

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) OUTPUT A CONTROL REGISTER (OACR) R252 - Read/Write Register Page: 10 Reset value: 0000 0000 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P Bits 7:6 = C0E[0:1]: COMP0 action bits . These ...

Page 106

MULTIFUNCTION TIMER (Cont’d) OUTPUT B CONTROL REGISTER (OBCR) R253 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P Bits 7:6 = C0E[0:1]: COMP0 Action Bits . These bits are set ...

Page 107

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) FLAG REGISTER (T_FLAGR) R254 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CP0 CP1 CM0 CM1 OUF Bit 7 = CP0: Capture 0 flag. This bit is set by hardware ...

Page 108

MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA MASK REGISTER (IDMR) R255 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 GT- CM0 CP0D CP0I CP1I IEN D Bit 7 = GTIEN: Global timer interrupt enable . This bit is set and ...

Page 109

MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) DMA ADDRESS POINTER REGISTER (DAPR) R241 - Read/Write Register Page: 9 Reset value: undefined 7 DAP DAP DAP5 DAP4 DAP3 DAP2 7 6 Bits 7:2 = DAP[7:2]: MSB of DMA address regis- ter ...

Page 110

MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA CONTROL REGISTER (IDCR) R243 - Read/Write Register Page: 9 Reset value: 1100 0111 (C7h) 7 DCT SWE CPE CME DCTS D N Bit 7 = CPE: Capture 0 EOB . This bit is set by hardware ...

Page 111

OSDRAM CONTROLLER 8.4 OSDRAM CONTROLLER 8.4.1 Introduction The OSDRAM Controller handles the interface be- tween the Display Controller, the CPU and the OS- DRAM. The time slots are allocated to each unit in order to optimize the response time. ...

Page 112

OSDRAM CONTROLLER (Cont’d) 8.4.2.1 Time Sharing during Display The time necessary to display a character on the screen defines the basic repetitive cycle of the OS- DRAM controller. This whole cycle represents therefore 18 clock periods. This cycle is divided ...

Page 113

OSDRAM CONTROLLER OSDRAM CONTROLLER (Cont’d) 8.4.3 OSDRAM Controller Reset Configuration During and after a reset, the OSDRAM access is disabled. When the OSDRAM controller is software disa- bled, it will: 1. Complete the current slot. 2. Complete any pending ...

Page 114

ON SCREEN DISPLAY CONTROLLER (OSD) 8.5.1 Introduction The OSD displays Closed Captioning (EIA708 specification) or other character data and menus screen. Each row can be defined through three different Display configurations: – Serial mode: each character ...

Page 115

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.3.1 Display Attributes Global screen attributes: – Border color – Border translucency – Turn all background color into border color Row parameters and attributes: – Row mode control (serial, basic parallel, ...

Page 116

OSD CONTROLLER (Cont’d) All colors are taken from a double Palette set (Background and Foreground) which are both OS- DRAM mapped and thus definable in real-time. The priority of all color layers is, from highest to lowest: Mouse, underline, foreground ...

Page 117

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.3.5 Cursor & Flash A cursor facility may be emulated under software control, using the “flash” attribute. This allows to have a “flash-on-word” in serial mode or a “flash- on-character” in ...

Page 118

OSD CONTROLLER (Cont’d) If the italic attribute is still active at the end of the row, the last character code to be displayed is truncated to the vertical position where it would have finished without the italic attribute. If the ...

Page 119

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.3.8 Scrolling The row RAM buffer architecture of the Display al- lows all scrolling operations to be performed very easily by software: scroll up, scroll down, scroll left, scroll right and ...

Page 120

OSD CONTROLLER (Cont’d) 8.5.3.11 Translucency Function The translucency feature is designed to provide a better OSD quality while displaying rows in mixed mode. Instead of forcing the background color of any character to any full intensity color, (which will pre- ...

Page 121

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) Figure 57. Digital Translucency Display Scheme using STV2238D in PQFP64 Package VIDEO PROCESSOR (STV2238D) Internal Red Contrast Internal Green Reduction Internal Blue TSLU Figure 58. Application Example using STV224x/228x in SDIP56 ...

Page 122

Mouse Pointer The Mouse Pointer icon is built as an 18x26 dot matrix fully user definable, selected from any of the OSD characters in Font ROM memory (ex- cept 00h). This allows a multiple mouse configura- tion. ...

Page 123

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) Vertical & Horizontal Sync Pulse Inputs A spike filter has been implemented on the vertical Sync input. This circuit is inserted after internal po- larity compensation of the VSYNC input signal ...

Page 124

OSD CONTROLLER (Cont’d) 8.5.5 Programming the Display The row-wise RAM buffer contains the description of the characters to display: – Row and character attributes (color, shape etc.) – Horizontal shift code – Character codes (addressing the Font ROM) While one ...

Page 125

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) Figure 59. OSDRAM Mapping OSDRAM 2n+b Row Buffer 2 2n 2p+a Row Buffer 1 2p 8Fh Buffer address, Mouse & Palette description section 00h Segment 22h Notes the start ...

Page 126

OSD CONTROLLER (Cont’d) 8.5.5.2 Row Buffer Description The start address for each buffer must be even. Starting from address 2p+6, write a string corre- sponding to the character codes and the possible attributes as in the example below: Basic Byte ...

Page 127

ON SCREEN DISPLAY CONTROLLER (OSD) Figure 60. Parallel Mode Mapping Examples Memory Segment = 22h Basic Parallel Mode 17Fh Free for user ECh EBh Palette Attribute 36 EAh Character Code 36 A7h Palette Attribute 2 Character Code 2 A6h ...

Page 128

OSD CONTROLLER (Cont’d) 8.5.5.5 Font ROM To address the characters in Font ROM refer to Figure 61. To obtain the character code, add the line code to the column code. Example 1: The code for the ‘A’ character is: Matrix ...

Page 129

... ON SCREEN DISPLAY CONTROLLER (OSD) Figure 61. ST92196A Font ROM Contents 129/268 ...

Page 130

OSD CONTROLLER (Cont’d) 8.5.5.6 Event Line Address in Segment 22h: 00h (Bits 15:8), 01h (Bits 7: EL[8: 9-bit number specifying at which TV line number the character row display should start. For ...

Page 131

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.6 Programming the Color Palettes The Palette attributes are coded inside the two Palettes (Basic background and foreground, and Extended background and foreground); they are therefore accessible in all modes, parallel ...

Page 132

OSD CONTROLLER (Cont’d) 8.5.6.1 Underline Color Set 1 (USC1) Address in Segment 22h: 04h (Bits 15:8), 05h (Bits 7:0) 15 U1T2 To support “windows-like” button effects, the color of the 2 ( 18x26 matrix) bottom dot lines of ...

Page 133

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.6.2 Underline Color Set 2 (UCS2) Address in Segment 22h: 06h (Bits 15:8), 07h (Bits 7: U2T2 Bits 15:12 = Free for the user Bits 11:9 ...

Page 134

OSD CONTROLLER (Cont’d) 8.5.6.3 Foreground Palettes FT2 The foreground palettes (Basic and Extended) both use the same principle: – The basic foreground palette is stored in OS- DRAM (segment 22h) starting from 10h to 2Fh (see ...

Page 135

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) Table 24. Underline Mode Control Bits Description Underline color for a 9x13 dot matrix underline Line 12: foreground color 0 1 ...

Page 136

OSD CONTROLLER (Cont’d) 8.5.6.4 Background Palettes 15 M BT2 The background palettes (Basic and Extended) both use the same principle: The basic background palette is stored in OS- DRAM (segment 22h) starting from 30h to 4Fh (see Figure 59). The ...

Page 137

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.7 Programming the Mouse Pointer The Mouse Pointer is programmed using two con- trol bits stored in registers, and three 16-bit words located in OSDRAM (Figure 59). The mouse pointer can ...

Page 138

OSD CONTROLLER (Cont’d) 8.5.7.1 Mouse Coding Data Address in Segment 22h: 08h (Bits 15:8), 09h (Bits 7:0) 15 MPFE MPRE MFC4 MFC3 MFC2 MFC1 MFC0 MPF8 MPF7 MPF6 Bit 15 = MPFE Mouse Pointer Fringe Enable bit This bit is ...

Page 139

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.7.2 Mouse Pointer Vertical Position Address in Segment 22h: 0Ah (Bits 15:8), 0Bh (Bits 7:0) 15 MDS Bit 15 = MDS Mouse Double Size enable bit This bit enables or disables ...

Page 140

OSD CONTROLLER (Cont’d) 8.5.7.3 Mouse Pointer Horizontal Position 15 Bits 15:8: are at address 0Ch in Segment 22h. Bits 7:0 are at address 0Dh Bits 15:11 = free for the user Bits 10:0 = MPX[10:0] Mouse Pointer horizontal position These ...

Page 141

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.8 Programming the Row Buffers The 2 row buffers are based on the same structure (Figure 59): – Next Buffer Start Address – Row Mode – Horizontal Shift – Row Character ...

Page 142

OSD CONTROLLER (Cont’d) 8.5.8.2 Horizontal Shift and Row Character Count Address in Segment 22h (Bits 15:8 (Bits 7:0). See 15 RCN5 RCN4 RCN3 RCN2 RCN1 RCN0 For each row to be displayed, the number ...

Page 143

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.8.3 Row Attributes Address in Segment 22h See For each row to be displayed, specify the font ma- trix used (9x13 or 18x26), ...

Page 144

OSD CONTROLLER (Cont’d) Bit 1 = ROU Rounding control bit This bit enables or disables the rounding for the whole row. 0: the rounding is disabled 1: the rounding is enabled Note: For a 18x26 matrix size, there is no ...

Page 145

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.8.5 Serial Mode In serial mode, only 1 byte is used to describe the character code or the attribute – If the most significant bit (Bit 7) of this byte is ...

Page 146

OSD CONTROLLER (Cont’d) Foreground Serial Attribute Address in Segment 22h See FLA IT FP3 Bit 5 = FLA Flash control bit This bit controls the flashing feature (see Section 0.2.4.2). 0: ...

Page 147

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) 8.5.8.7 Extended Parallel Mode In extended parallel mode, each character code (1 byte) is followed by a palette attribute (1 byte) and a shape attribute (1 byte). Refer to Let’s assume ...

Page 148

OSD CONTROLLER (Cont’d) SHAPE ATTRIBUTE - 9x13 MATRIX Address in segment 22h: 2p+5+3z. See 7 CODX SPL1 SPL0 FXP BXP Bit 7 = CODX Character Code Extension This bit is used with SPL[1:0] as the character ad- dress extension. Thus ...

Page 149

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) SHAPE ATTRIBUTE - 18x26 MATRIX Address in segment 22h: 2p+5+3z. See 7 CODX DBLY DBLX FXP BXP Bit 7 = CODX Character Code Extension This bit is used as the character ...

Page 150

OSD CONTROLLER (Cont’d) 8.5.8.8 Row Buffer Management To Start the Display: 0. Write the (DION, OSDE) bits to (1,0) to access the OSDRAM with the CPU clock, 1. Initialize the color palettes, 2. Initialize the Mouse Pointer Data (if needed), ...

Page 151

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) The real time control provides: – A continuous search of matching values be- tween Scan line and Event Line (this condition being evaluated at each TV line start). – A display ...

Page 152

OSD CONTROLLER (Cont’d) 8.5.9 Register Description To run the Display controller properly, you need to program the 7 registers that configure the display BORDER COLOR REGISTER 2 (OSDBCR2) R246 - Read/Write Register Page: 42 Reset Value: 0x00 0000 7 B2BC ...

Page 153

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) ENABLE REGISTER (OSDER) R248 - Read/Write Register Page: 42 Reset Value: 0000 0000 (00h) 7 DION OSDE TE DBLS NIDS Bit 7 = DION Display ON This bit is used in ...

Page 154

OSD, time 0 1 on, Pixel clock control on, Pixel clock fully SCREEN DISPLAY CONTROLLER (OSD) The Display is partially enabled. The OSDRAM control- ler is running with the Pixel clock, allowing CPU ...

Page 155

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) Bit 3 = NIDS Non Interlaced Display control bit This bit selects the interlaced or non-interlaced mode. 0: The display works in interlaced mode (line counting, fringe and rounding algorithms are ...

Page 156

OSD CONTROLLER (Cont’d) DELAY REGISTER (OSDDR) R249 - Read/Write Register Page: 42 Reset Value: 0xxx xxxx 7 PASW HPOL VPOL FBPOL VD3 Note: The display may flicker if you write to the Delay Register while OSD is fully on. Bit ...

Page 157

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) FLAG BIT REGISTER (OSDFBR) R250 - Read/Write Register Page: 42 Reset Value: xxxx xxxx (xxh) 7 BUFL VSY HSY VSDL FIELD Bit 7 = BUFL Buffer Flag bit This bit indicates ...

Page 158

OSD CONTROLLER (Cont’d) SCAN LINE REGISTER (OSDSLR) R251 - Read Only Register Page: 42 Reset Value: xxxx xxxx (xxh) 7 SL7 SL6 SL5 SL4 SL3 Bits 7:0 = SL[7:0] Scan Line Counter Value These bits indicate the current vertical position ...

Page 159

ON SCREEN DISPLAY CONTROLLER (OSD) OSD CONTROLLER (Cont’d) Table 33. OSD Register Map Register Register Number 7 Name Page 42 246 OSDBCR2 B2BC 247 OSDBCR1 DIFB 248 OSDER DION 249 OSDDR PASW 250 OSDFBR BUFL 251 OSDSLR SL7 252 ...

Page 160

CLOSED CAPTION DATA SLICER (DS) 8.6.1 Introduction Depending on the ST9 device, one or two Data Slicers may be available in the MCU (refer the de- vice feature list and Register map). Each Data Slicer can extract either Closed ...

Page 161

CLOSED CAPTION DATA SLICER (DS) DATA SLICER (Cont’d) 8.6.3 Data Slicer Operation The data slicer is enabled or disabled using the EDS bit in the DR1 register. The Data Slicer clock frequencies are generated by the clock generator starting ...

Page 162

DATA SLICER (Cont’d) Figure 68. Data Slicer Waveforms GEMSTAR SIGNAL (DSOUT) CLOSED CAPTION SIGNAL (DSOUT) CLOCK RUN-IN WINDOW FRAME CODE WINDOW HORIZONTAL SYNC (CSYNC) INTERRUPT IRQ CCIRQ for IRQ_INV=1 CCIRQ for IRQ_INV=0 - CLOSED CAPTION DATA SLICER (DS) Clock run-in ...

Page 163

CLOSED CAPTION DATA SLICER (DS) DATA SLICER (Cont’d) 8.6.4 Interrupt handling If the device has two data slicers, both use the same interrupt channel. So some additional soft- ware is needed, when using both slicers at the same time. ...

Page 164

DATA SLICER (Cont’d) 8.6.5 Register Description The register description lists the register page for Data Slicer 0 (DS0 second Data Slicer is avail- able (DS1 mapped in Page 46. DATA REGISTER 1 (DR1) R240 - Read ...

Page 165

CLOSED CAPTION DATA SLICER (DS) DATA SLICER (Cont’d) DATA REGISTER 4 (DR4) R243 - Read only Register Page: 45 Reset Value: 0000 0000 (00h) 7 D4.7 D4.6 D4.5 D4.4 D4.3 D4.2 D4.1 D4.0 Bit 7:0 = D4[7:0]: Fourth data ...

Page 166

DATA SLICER (Cont’d) Bit 4 = SEARCH: Enhanced Signal Search. This bit is set and cleared by software. This bit should be set to improve the reliability of properly identifying signals in closed caption and Gemstar format when doing a ...

Page 167

CLOSED CAPTION DATA SLICER (DS) Table 34. DS Register Map Register Register Number 7 Name Page 45 240 DR1 D1.7 241 DR2 D2.7 242 DR3 D3.7 243 DR4 D4.7 244 CR1 STNDBY 245 CR2 EDS 246 MR CCMODE 167/268 ...

Page 168

VIDEO SYNC ERROR DETECTOR (SYNCERR) 8.7.1 Functional Description The Sync Error Detector provides information to the tuning system whether an IF signal is a picture carrier or not. The CSYNC source for the detector is selected using the SYSEL[1:0] ...

Page 169

IR PREPROCESSOR (IR) 8.8 IR PREPROCESSOR (IR) 8.8.1 Functional Description The IR Preprocessor measures the interval be- tween adjacent edges of the demodulated output signal from the IR amplifier/detector. You can specify the polarity using the POSED and NEGED ...

Page 170

FOUR-CHANNEL I C BUS INTERFACE (I2C) 8.9.1 Introduction 2 The I C Bus Master/Slave Interface supports serial I C buses used for communication with various external devices. It meets all of the re- 2 ...

Page 171

FOUR-CHANNEL I C BUS INTERFACE (I2C BUS INTERFACE (Cont’d) 8.9.2 General Description In addition to receiving and transmitting data, this interface convert them from serial to parallel for- mat and vice versa. The interface is ...

Page 172

I C BUS INTERFACE (Cont’d) 8.9.3 Functional Description Refer to Section 8.9.6 for the bit definitions. Figure 70 gives the block diagram of the cell default, the I C interface is in inactive slave mode, except when ...

Page 173

FOUR-CHANNEL I C BUS INTERFACE (I2C BUS INTERFACE (Cont’d) 8.9.3.2 Slave Mode As soon as a start condition is detected, the ad- dress is received from the SDA line and sent to the shift register; ...

Page 174

I C BUS INTERFACE (Cont’d) Master Receiver Following the address transmission and acknowl- edgment, the master receives bytes from the SDA line into the I2CDR register via the internal shift register. After each byte the interface generates in sequence: ...

Page 175

FOUR-CHANNEL I C BUS INTERFACE (I2C BUS INTERFACE (Cont’d) 8.9.6 Register Description OWN ADDRESS REGISTER (I2COAR) R240 - Read/Write Register Page: 44 Reset Value: 0000 0000(00h) 7 ADR7 ADR6 ADR5 ADR4 ADR3 Bit 7:1 = ...

Page 176

I C BUS INTERFACE (Cont’d) FREQUENCY REGISTER (I2CFQR) R241 - Read/Write Register Page: 44 Reset Value: 0000 0000(00h) 7 BUS_S0 BUS_S1 FMEN PP_DRV Q3 2 Bits 7:6 = BUS_S[1: BUS Selection bits 2 These bits connect the ...

Page 177

FOUR-CHANNEL I C BUS INTERFACE (I2C BUS INTERFACE (Cont’d) CONTROL REGISTER (I2CCTR) R242 - Read/Write Register Page: 44 Reset Value: 0000 0001(01h) 7 GENC_ SEND_ MONI AFEN RTI ACK ACK TOR Bit 7 = AFEN ...

Page 178

I C BUS INTERFACE (Cont’d) DATA REGISTER (I2CDR) R243 - Read/Write Register Page: 44 Reset Value: 0000 0000(00h) 7 SR8 SR7 SR6 SR5 SR4 Bit 7:0 = SR[8:1] address or data byte These bits contains the address or data ...

Page 179

FOUR-CHANNEL I C BUS INTERFACE (I2C BUS INTERFACE (Cont’d) Bit 1 = UNEXP Unexpected flag bit This bit is useful for error detection in a multimas- ter mode system, when a master is continuing its ...

Page 180

I C BUS INTERFACE (Cont’d) Bit 6 = ARB_LOST Arbitration LOST detection bit This bit indicates if an arbitration lost occurred on the bus arbitration lost occurred 1: An arbitration lost occurred. The bit is set when ...

Page 181

FOUR-CHANNEL I C BUS INTERFACE (I2C BUS INTERFACE (Cont’d) Table 37. I2C Interface Register Map and Reset Values Register Address 7 Name I2COAR 240 ADR7 Reset Value I2CFQR 241 BUS_S0 Reset Value I2CCTR 242 AFEN ...

Page 182

SERIAL PERIPHERAL INTERFACE (SPI) 8.10.1 Introduction The Serial Peripheral Interface (SPI general purpose on-chip shift register peripheral. It allows communication with external peripherals via an SPI protocol bus. In addition, special operating modes allow re- duced software ...

Page 183

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 8.10.3 Functional Description The SPI, when enabled, receives input data from the internal data bus to the SPI Data Register (SPIDR). A Serial Clock (SCK) is generated by controlling through software ...

Page 184

SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 73. SPI I/O Pins n SCK SDO SDI PORT BIT LATCH PORT BIT LATCH PORT BIT LATCH INT2 - SERIAL PERIPHERAL INTERFACE (SPI) 8.10.4 Interrupt Structure The SPI peripheral is associated with external in- terrupt ...

Page 185

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 8.10.5 Working With Other Protocols The SPI peripheral offers the following facilities for 2 operation with S-bus/I C-bus and IM-bus proto- cols: Interrupt request on start/stop detection Hardware clock synchronisation Arbitration ...

Page 186

SERIAL PERIPHERAL INTERFACE (Cont’d) 2 Table 39. Typical I C-bus Sequences Phase SPICR.CPOL, CPHA = 0, 0 SPICR.SPEN = 0 SPICR.BMS = 1 INITIALIZE SCK pin set as AF output SDI pin set as input Set SDO port bit to ...

Page 187

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) The data on the SDA line is sampled on the low to high transition of the SCL line. 2 SPI working with an I C-bus 2 To use the SPI with ...

Page 188

SERIAL PERIPHERAL INTERFACE (Cont’d) 8.10.7 S-Bus Interface The S-bus is a three-wire bidirectional data-bus, possessing functional features similar to the I 2 bus. As opposed to the I C-bus, the Start/Stop conditions are determined by encoding the infor- mation on ...

Page 189

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 8.10.8 IM-bus Interface The IM-bus features a bidirectional data line and a clock line; in addition, it requires an IDENT line to distinguish an address byte from a data byte 2 ...

Page 190

SERIAL PERIPHERAL INTERFACE (Cont’d) 8.10.9 Register Description It is possible to have independent SPIs in the same device (refer to the device block dia- gram). In this case they are named SPI0 thru SPI2. If the device ...

Page 191

SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Bit 2 = CPHA: Transmission Clock Phase. CPHA controls the relationship between the data on the SDI and SDO pins, and the clock signal on the SCK pin. The CPHA bit ...

Page 192

SERIAL COMMUNICATIONS INTERFACE (SCI) 8.11.1 Introduction The Serial Communications Interface (SCI) offers full-duplex asynchronous serial data exchange for interfacing a wide range of external equipment. It has the following principal features: Full duplex asynchronous operation. Transmit, receive, line status, ...

Page 193

SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 83. SCI Functional Schematic RX buffer register RX shift INTCLK register LBEN Baud rate generator TX shift register TX buffer register 8.11.2 SCI Operation Each data bit is sampled 16 ...

Page 194

SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.11.3.1 Data transfer Data to be transmitted by the SCI is first loaded by the program into the Transmitter Buffer Register. The SCI will transfer the data into the Transmitter Shift Register when the Shift Register ...

Page 195

SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.11.4 Clocks And Serial Transmission Rates The communication bit rate of the SCI transmitter and receiver sections is provided from the internal Baud Rate Generator divided by 16. x Baud Rate ...

Page 196

SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 41. Practical Example of SCI Baud Rate Generator Divider Values Baud Clock Desired Freq Rate Factor 50. 75. 110. 300. 600. 1200. 2400.00 ...

Page 197

SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.11.6 Input Signals SIN: Serial Data Input. This pin is the serial data input to the SCI receiver shift register. 8.11.7 Output Signals SOUT: Serial Data Output. This Alternate Func- tion ...

Page 198

SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 43. SCI Interrupt Vectors Interrupt Source Transmitter Buffer or Shift Register Empty Transmit DMA end of Block Received Data Pending Receive DMA end of Block Break Detector Address Word Match Receiver Error Figure 90. SCI ...

Page 199

SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.11.8.2 DMA Two DMA channels are associated with the SCI, for transmit and for receive. These follow the reg- ister scheme as described in the DMA chapter. DMA Reception To perform ...

Page 200

SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.11.9 Register Description The SCI registers are located in the following pag the ST9: SCI number 0: page 24 (18h) SCI number 1: page 25 (19h) (when present) The SCI is controlled by the ...