CY24271 Cypress Semiconductor Corporation., CY24271 Datasheet - Page 8

• Manufacturer Part Number: CY24271
• Description: Rambus Xdr Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

AC Operating Conditions
The AC operating conditions follow.
DC Electrical Specifications
Document Number: 001-00411 Rev. *B
Notes
t
t
t
t
Δt
p
f
t
C
C
f
V
V
V
V
I
I
I
I
I
V
I
I
Z
10. Jitter measured at crossing points and is the absolute value of the worst case deviation.
11. Measured at crossing points.
12. If input modulation is used; input modulation is allowed but not required.
13. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated
14. V
15. V
16. V
17. I
CYCLE,IN
JIT,IN(cc)
DCIN
RIN
MIN
SR,IN
SCL
DD
DD
DD
OL/
OL,ABS
OL,SDA
OZ
18. Minimum I
19. Z
Parameter
Parameter
MIN
OX
COS
OL,ABS
ISET
OL,SDA
OUT
IN,REF
IN,CMOS
RIN
[7]
[7]
[7]
by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
I
[12]
REF
[7]
REF
/ t
OUT
[12]
OX
COS
OL_ABS
[11]
[7]
/ t
FIN
is measured on external divider network.
is equal to V
FIN
is defined at the output pins as (0.94V – 0.90V)/(I
= (clock output high voltage – clock output low voltage), measured on the external divider network.
is measured at the clock output pins of the package.
OL,ABS
REFCLK, REFCLKB input cycle time
Input Cycle to Cycle Jitter
Input Duty Cycle
Rise and Fall Times
Rise and Fall Times Difference
Modulation Index for triangular modulation
Modulation Index for non-triangular modulation
Input Frequency Modulation
Input Slew Rate (measured at 20%–80% of
input voltage) for REFCLK
Capacitance at REFCLK inputs
Capacitance at CMOS inputs
SMBus clock frequency input in SCL pin
Differential output crossing point voltage
Output voltage swing (peak-to-peak single-ended)
Absolute output low voltage at CLK[3:0], CLK[3:0]B
Reference voltage for swing controlled current, I
Power Supply Current at 2.625V, f
Power Supply Current at 2.625V, f
Power Supply Current at 2.625V, f
Ratio of output low current to reference current
Minimum current at V
SDA output low voltage at test condition of SDA output low current = 4 mA
SDA output low voltage at test condition of SDA voltage = 0.8V
Current during High Z per pin at CLK[3:0], CLK[3:0]B
Output dynamic impedance when clock output signal is at V
ISET
is measured at the clock output pin with R
/R
RC
.
Description
[7]
OL,ABS
[10]
[18]
Description
0.94
ref
ref
ref
– I
RC
= 100 MHz, and f
= 133 MHz, and f
= 133 MHz, and f
0.90
= 148 ohms or less.
) under conditions specified for I
[14]
[17]
REF
REFSEL = 0, /BYPASS = High
REFSEL = 1, /BYPASS = High
/BYPASS = Low
Over 10,000 cycles
Measured at 20%–80% of input
voltage for REFCLK and
REFCLKB inputs
[15]
[16]
out
out
out
= 300 MHz
= 667 MHz
= 800 MHz
OL
Condition
= 0.9V
OL, ABS
[19]
.
1000
0.85
0.98
Min
300
0.9
6.8
45
–
–
–
–
6
–
40%
Min
Typ
325
175
DC
1.0
1.0
7.0
30
9
7
4
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
0.5
Max
1.02
60%
Max
350
125
130
185
700
150
100
1.1
7.2
0.4
0.6
85
10
11
33
10
–
–
–
–
8
–
4
7
[13]
CY24271
t
CYCLE
Unit
V/ns
Unit
mV
mA
mA
mA
mA
mA
kHz
kHz
Page 8 of 13
μA
pF
pF
Ω
ns
ns
ns
ps
ps
ps
V
V
V
V
%
%
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