CY24271 Cypress Semiconductor Corporation., CY24271 Datasheet - Page 4

• Manufacturer Part Number: CY24271
• Description: Rambus Xdr Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Table 4. Modes of Operation for CY24271
SMBus Protocol
The CY24271 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
DC specifications are modified to RAMBUS standard to support
1.8, 2.5, and 3.3 volt devices. Time-out detection and packet
error protocol SMBus features are not supported.
Input Clock Signal
The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).
When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in
DC Operating Conditions
tions
Document Number: 001-00411 Rev. *B
Notes
4. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
5. Default mode of operation is at power up.
EN
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
on page 8.
/BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
0
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[5]
on page 7 and
1
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
[5]
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
[5]
AC Operating Condi-
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
[5]
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
[5]
REFCLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
REFCLK/
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in
voltage V
point of REFCLK. For the range of V
Conditions
Operating Conditions tables.
SMBus Data Byte Definitions
Three data bytes are defined for the CY24271. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
The definition of Byte 2 is shown in
on page
device and the lower three bits are the ID numbers assigned to
the vendor by Rambus.
[4]
5. The upper five bits are the revision numbers of the
TH
on page 7, the outputs also meet the DC and AC
CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B
at the REFCLKB pin. This determines the proper trip
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
REFCLKB
Reserved for Vendor Test
REFCLK/
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
REFCLKB
REFCLK/
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
Figure
Table
TH
specified in
2, provide a reference
5,
Table
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
REFCLKB
REFCLK/
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
CY24271
6, and
DC Operating
Page 4 of 13
Table 7
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