CY24271 Cypress Semiconductor Corporation., CY24271 Datasheet - Page 3

• Manufacturer Part Number: CY24271
• Description: Rambus Xdr Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

PLL Multiplier
Table 2
Default multiplier at power up is 4.
Table 2. PLL Multiplier Selection
Device ID and SMBus Device Address
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address designates a
write or read operation.
CY24271 devices on the same SMBus.
Modes of Operation
The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
Table 3. SMBus Device Addresses for CY24271
Document Number: 001-00411 Rev. *B
Notes
1. Output frequencies shown in
2. Default PLL multiplier at power up.
3. Contact the factory if operation at these frequencies is required.
MULT2
Device
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.
0
0
0
0
1
1
1
1
0
1
2
3
shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.
Register
MULT1
XCG
0
0
1
1
0
0
1
1
Operation
MULT0
Read
Read
Read
Read
Write
Write
Write
Write
0
1
0
1
0
1
0
1
Table 3
Table 2
Frequency Multiplier
are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum
shows the addresses for four
Address
Hex
DA
DB
DC
DD
DE
D8
D9
DF
15/2
15/4
9/2
3
4
5
6
8
1
Five Most Significant Bits
REFCLK = 100 MHz
1
8-bit SMBus Device Address Including Operation
0
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.
Table 4
Outputs Disabled Mode (EN = low), and Bypass Mode (EN =
high, /BYPASS = low). There is an option reserved for vendor
test. Disabled outputs are set to High Z.
At power up, the SMBus registers default to the last entry in
Table
RegC, and RegD are all ‘1’. Thus, all outputs are controlled by
the logic applied to EN and /or BYPASS.
400
300
500
600
800
450
750
375
1
[2]
4. The value at RegTest is 0. The values at RegA, RegB,
[1]
shows selection from one to all four of the outputs, the
, REFSEL = 0 REFCLK = 133 MHz
Output Frequency (MHz)
1
ID1
0
0
1
1
ID0
0
1
0
1
1067
1000
533
400
667
800
600
500
WR# / RD
[3]
[3]
[3]
[1]
, REFSEL = 1
0
1
0
1
0
1
0
1
CY24271
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