DSPIC33FJ64GS406 Microchip Technology Inc., DSPIC33FJ64GS406 Datasheet - Page 47

• Manufacturer Part Number: DSPIC33FJ64GS406
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

4.0
The
dsPIC33FJ64GS406/606/608/610 architecture features
separate program and data memory spaces and buses.
This architecture also allows the direct access to program
memory from the data space during code execution.
FIGURE 4-1:
 2010 Microchip Technology Inc.
Note:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
dsPIC33FJ32GS406/606/608/610
MEMORY ORGANIZATION
dsPIC33FJ32GS406/606/608/610
This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the dsPIC33F/PIC24H
Family Reference Manual, “Section 4.
Program Memory” (DS70202), which is
available from the Microchip web site
(www.microchip.com).
Alternate Vector Table
Interrupt Vector Table
Device Configuration
(11008 instructions)
GOTO Instruction
Unimplemented
Reset Address
Flash Memory
User Program
(Read ‘0’s)
Registers
DEVID (2)
Reserved
Reserved
Reserved
Reserved
dsPIC33FJ64GS406/606/608/610
PROGRAM MEMORY MAPS FOR dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 DEVICES
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0057FE
0x005800
0x7FFFFE
0x800000
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFF0002
0xFFFFFE
and
Preliminary
4.1
The
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ64GS406/606/608/610
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ64GS406/606/608/610 devices are shown
in Figure 4-1.
program
Program Address Space
dsPIC33FJ64GS406/606/608/610
memory
Alternate Vector Table
Interrupt Vector Table
Device Configuration
(21760 instructions)
address
GOTO Instruction
Unimplemented
Reset Address
Flash Memory
User Program
(Read ‘0’s)
Registers
DEVID (2)
Reserved
Reserved
Reserved
Reserved
maps
memory
DS70591C-page 47
devices
space
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x00ABFE
0x00AC00
0x7FFFFE
0x800000
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFF0002
0xFFFFFE
for
of
is
and
and
the
the
4M