DSPIC33FJ64GS406 Microchip Technology Inc., DSPIC33FJ64GS406 Datasheet - Page 229

• Manufacturer Part Number: DSPIC33FJ64GS406
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 16-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4
SYNCEN
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
R/W-0
R/W-0
PTEN
(1)
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
EIPU: Enable Immediate Period Updates bit
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCIx/SYNCO1 polarity is inverted (active-low)
0 = SYNCIx/SYNCO1 is active-high
SYNCOEN: Primary Time Base Sync Enable bit
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
SYNCEN: External Time Base Synchronization Enable bit
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
SYNCSRC<2:0>: Synchronous Source Selection bits
000 = SYNCI1
001 = SYNCI2
010 = SYNCI3
011 = SYNCI4
100 = Reserved
101 = Reserved
111 = Reserved
R/W-0
U-0
—
PTCON: PWM TIME BASE CONTROL REGISTER
SYNCSRC<2:0>
HC = Cleared in Hardware HS = Set in Hardware
W = Writable bit
‘1’ = Bit is set
PTSIDL
R/W-0
R/W-0
(1)
HS/HC-0
SESTAT
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
SEIEN
R/W-0
R/W-0
(1)
(1)
(1)
(1)
EIPU
R/W-0
R/W-0
SEVTPS<3:0>
(1)
SYNCPOL
x = Bit is unknown
R/W-0
R/W-0
(1)
DS70591C-page 229
(1)
SYNCOEN
R/W-0
R/W-0
bit 8
bit 0
(1)