DSPIC33FJ64GS406 Microchip Technology Inc., DSPIC33FJ64GS406 Datasheet - Page 245

• Manufacturer Part Number: DSPIC33FJ64GS406
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 16-19: IOCONx: PWM I/O CONTROL REGISTER (CONTINUED)
 2010 Microchip Technology Inc.
bit 3-2
bit 1
bit 0
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings.
CLDAT<1:0>: State
FCLCONx<IFLTMOD> = 0: Normal Fault mode
If current-limit active, then CLDAT<1> provides state for PWMxH
If current-limit active, then CLDAT<0> provides state for PWMxL
FCLCONx<IFLTMOD> = 1: Independent Fault mode
CLDAT<1:0> is ignored
SWAP: SWAP PWMxH and PWMxL pins bit
1 = PWMxH output signal is connected to PWMxL pins; PWMxL output signal is connected to PWMxH
0 = PWMxH and PWMxL pins are mapped to their respective pins
OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0 = Output overrides via the OVDDAT<1:0> bits occur on next CPU clock boundary
pins
(2)
for PWMxH and PWMxL Pins if CLMOD is Enabled bits
Preliminary
DS70591C-page 245