DSPIC33FJ64GS406 Microchip Technology Inc., DSPIC33FJ64GS406 Datasheet - Page 256
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DSPIC33FJ64GS406
Manufacturer Part Number
DSPIC33FJ64GS406
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ64GS406.pdf
(418 pages)
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 17-1:
DS70591C-page 256
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-8
bit 7
bit 6
Note 1: CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’.
CNTERR
SWPAB
R/W-0
R/W-0
2: Read-only bit when QEIM<2:0> = ‘1XX’. Read/write bit when QEIM<2:0> = ‘001’.
3: Prescaler utilized for 16-bit Timer mode only.
4: This bit applies only when QEIM<2:0> = 100 or 110.
5: When configured for QEI mode, this control bit is a ‘don’t care’.
CNTERR: Count Error Status Flag bit
1 = Position count error has occurred
0 = No position count error has occurred
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
INDEX: Index Pin State Status bit (Read-Only)
1 = Index pin is High
0 = Index pin is Low
UPDN: Position Counter Direction Status bit
1 = Position Counter Direction is positive (+)
0 = Position Counter Direction is negative (-)
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111 = Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match
110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter
101 = Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match
100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter
011 = Unused (Module disabled)
010 = Unused (Module disabled)
001 = Starts 16-bit Timer
000 = Quadrature Encoder Interface/Timer off
SWPAB: Phase A and Phase B Input Swap Select bit
1 = Phase A and Phase B inputs swapped
0 = Phase A and Phase B inputs not swapped
PCDOUT: Position Counter Direction State Output Enable bit
1 = Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin)
0 = Position Counter Direction Status Output Disabled (Normal I/O pin operation)
PCDOUT
R/W-0
U-0
—
QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2)
(MAXxCNT)
(MAXxCNT)
W = Writable bit
‘1’ = Bit is set
QEISIDL
TQGATE
R/W-0
R/W-0
INDEX
R/W-0
R-0
Preliminary
TQCKPS<1:0>
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
R/W-0
UPDN
R/W-0
POSRES
R/W-0
R/W-0
2010 Microchip Technology Inc.
x = Bit is unknown
QEIM<2:0>
R/W-0
R/W-0
TQCS
UPDN_SRC
R/W-0
R/W-0
bit 8
bit 0
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