DSPIC33FJ64GS406 Microchip Technology Inc., DSPIC33FJ64GS406 Datasheet - Page 177

• Manufacturer Part Number: DSPIC33FJ64GS406
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

8.0
TABLE 8-1:
 2010 Microchip Technology Inc.
INT0 – External Interrupt 0
IC1 – Input Capture 1
IC2 – Input Capture 2
IC3 – Input Capture 3
IC4 – Input Capture 4
OC1 – Output Compare 1 Data
OC1 – Output Compare 1 Secondary Data
OC2 – Output Compare 2 Data
OC2 – Output Compare 2 Secondary Data
OC3 – Output Compare 3 Data
OC3 – Output Compare 3 Secondary Data
OC4 – Output Compare 4 Data
OC4 – Output Compare 4 Secondary Data
TMR2 – Timer2
TMR3 – Timer3
TMR4 – Timer4
TMR5 – Timer5
SPI1 – Transfer Done
SPI2 – Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
ECAN1 – RX Data Ready
ECAN1 – TX Data Request
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: This data sheet summarizes the features
Peripheral to DMA Association
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA)
of the dsPIC33FJ32GS406/606/608/610
and
family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
22. “Direct Memory Access (DMA)”
(DS70182) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
dsPIC33FJ64GS406/606/608/610
DMAxREQ Register
IRQSEL<6:0> Bits
Preliminary
0000000
0000001
0000101
0100101
0100110
0000010
0000010
0000110
0000110
0011001
0011001
0011010
0011010
0000111
0001000
0011011
0011100
0001010
0100001
0001011
0001100
0011110
0011111
0100010
1000110
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., the UART Receive register and Input Capture 1
buffer) and buffers or variables stored in RAM, with
minimal CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and, therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The peripherals that can utilize DMA are listed in
Table 8-1 along with their associated Interrupt Request
(IRQ) numbers.
Note:
Values to Read From
DMAxPAD Register
0x0226 (U1RXREG)
0x0236 (U2RXREG)
0x0148C (IC4BUF)
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0140 (IC1BUF)
0x0144 (IC2BUF)
0x0148 (IC3BUF)
0x0440 (C1RXD)
The DMA module is not available on
dsIPC33FJ32GS406/606/608/610
dsPIC33FJ64GS406 devices.
Peripheral
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DMAxPAD Register
0x0224 (U1TXREG)
0x0234 (U2TXREG)
Values to Write to
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x018C (OC3RS)
0x0180 (OC1RS)
0x0186 (OC2RS)
0x0192 (OC4RS)
0x0442 (C1TXD)
0x018E (OC3R)
0x0182 (OC1R)
0x0188 (OC2R)
0x0194 (OC4R)
DS70591C-page 177
Peripheral
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and