MC56F8366 Freescale Semiconductor, Inc, MC56F8366 Datasheet - Page 3
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MC56F8366
Manufacturer Part Number
MC56F8366
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F8366.pdf
(184 pages)
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56F8366/56F8166 General Description
Note: Features in italics are NOT available in the 56F8166 device.
Freescale Semiconductor
Preliminary
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
• Access up to 1MB of off-chip program and data memory
• Chip Select Logic for glueless interface to ROM and
• 512KB of Program Flash
• 4KB of Program RAM
• 32KB of Data Flash
• 32KB of Data RAM
• 32KB of Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
C-efficient architecture
SRAM
3
3
3
4
4
4
5
4
4
4
4
2
2
6
6
VREF
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOC
Fault Inputs
AD0
AD1
AD0
AD1
Temp_Sense
Decoder 0 or
Decoder 1 or
Quadrature
Quadrature
Timer D or
Timer A or
Timer B or
Timer C or
FlexCAN
SPI1 or
GPIOE
GPIOC
GPIOC
GPIOE
Quad
Quad
Quad
Quad
ADCA
ADCB
Decoding
Peripherals
Program Memory
256K x 16 Flash
16K x 16 Flash
16K x 16 Flash
16K x 16 RAM
D
2K x 16 RAM
SPI0 or
GPIOE
Boot ROM
ata Memory
4
PWMA
PWMB
56F8366/56F8166 Block Diagram - 144 LQFP
Memory
SCI1 or
GPIOD
2
RSTO
Hardware Looping Unit
Program Controller
Device Selects
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
Peripheral
RESET
SCI0 or
GPIOE
EMI_MODE
and
2
56F8366 Technical Data, Rev. 6
EXTBOOT
PAB
PDB
CDBR
CDBW
Watchdog
IPBus Bridge (IPBB)
COP/
RW
Control
EOnCE
Generation Unit
JTAG/
Port
Address
5
IRQA IRQB
Controller
IPAB
Interrupt
V
2
PP
56800E Core
IPWDB
V
16-Bit
4
Three 16-bit Input Registers
CAP
16 x 16 + 36 -> 36-Bit MAC
Four 36-bit Accumulators
System Bus
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional On-Chip Regulator
• Up to two FlexCAN modules
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four General Purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
• Up to 62 GPIO lines
• 144-pin LQFP Package
7
Integration
V
Control
System
Digital Reg
Data ALU
OCR_DIS
Module
DD
IPRDB
unobtrusive, real-time debugging
CLKO
Clock
resets
5
Low Voltage
R/W Control
V
Supervisor
SS
O
R
P
2
V
Analog Reg
DDA
CLKMODE
Generator
Clock
Manipulation
PLL
External Data
EMI CS or
FlexCAN2
Address Bus
Bus Control
GPIO or
Bus Switch
V
Unit
Bit
External
SSA
Switch
O
S
C
XTAL
EXTAL
6
2
8
7
9
GPIOD1 (CS3 or CAN2_RX)
GPIOD0 (CS2 or CAN2_TX)
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
PS / CS0 (GPIOD8)
DS / CS1 (GPIOD9)
3