MC56F8366 Freescale Semiconductor, Inc, MC56F8366 Datasheet
MC56F8366
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MC56F8366 Summary of contents
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... Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8366 Rev. 6 01/2007 freescale.com ...
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Version History Rev 0 Pre-release, Alpha customers only Rev 1.0 Initial Public Release Rev 2.0 Added output voltage maximum value and note to clarify in life expectancy note, since life expectancy is dependent on customer usage and must be determined ...
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General Description Note: Features in italics are NOT available in the 56F8166 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 1MB of off-chip ...
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Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56F8366/56F8166 Features . . . . . . . . . . ...
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Part 1 Overview 1.1 56F8366/56F8166 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • ...
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Memory Note: Features in italics are NOT available in the 56F8166 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume ...
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Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) • two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8366, SPI1 can also ...
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Features The 56F8366 hybrid controller includes 512KB of Program Flash and 32KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 32KB of Data RAM. It also supports program execution from external ...
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Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes and the Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the ...
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Architecture Block Diagram Note: Features in italics are NOT available in the 56F8166 device and are shaded in the following figures. The 56F8366/56F8166 architecture is shown in 56800E system buses communicate with internal memories, the external memory interface and ...
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JTAG / EOnCE 56800E CHIP TAP Controller TAP Linking Module External JTAG Port xdb2_m[15:0] NOT available on the 56F8166 device. Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is accomplished by the I/O to ...
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CLKGEN (OSC/PLL) Timer A 4 Quadrature Decoder 0 2 Timer D Timer B 4 Quadrature Decoder NOT available on the 56F8166 device. 12 To/From IPBus Bridge SPI 1 GPIOA GPIOB GPIOC GPIOD ch3i GPIOE ch3o GPIOF ...
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Name pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory ...
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... Details any chip issues that might be present Logic State True False True False 56F8366 Technical Data, Rev. 6 Centers, or online Order Number DSP56800ERM MC56F8300UM MC56F83xxBLUM MC56F8366 MC56F8366E MC56F8166E Signal State 1 Voltage Asserted Deasserted Asserted ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8366 and 56F8166 are organized into functional groups, as detailed in Table 2-1 and as illustrated in present on a pin. Table 2-1 Functional Group Pin Allocations ...
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V Power V Power DDA_ADC V Power DDA_OSC_PLL Ground V Ground SSA_ADC OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL EXTAL and Clock (GPIOA8 - 13) External A6 - ...
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Power V DDA_ADC Power V DDA_OSC_PLL Power Ground V SSA_ADC Ground OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL and Clock (GPIOA8 - External (GPIOE2 - ...
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Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Note: Signals in italics are NOT available in the 56F8166 device. If the “State During Reset” lists more than ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type V 103 Supply SSA_ADC OCR_DIS 79 Input Supply CAP V 2 128 CAP CAP CAP V ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type CLKO 3 Output A0 138 Output (GPIOA8) Input/ Output A1 10 (GPIOA9 (GPIOA10 (GPIOA11 (GPIOA12 (GPIOA13) 20 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type A6 17 Output (GPIOE2) Schmitt Input Output (GPIOE3 Output (GPIOA0) Schmitt Input Output (GPIOA1) A10 21 (GPIOA2) A11 22 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type GPIOB0 33 Schmitt Input/ Output (A16) Output D0 59 Input/ Output (GPIOF9) Input/ Output D1 60 (GPIOF10 (GPIOF11 (GPIOF12 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type D7 28 Input/ Output (GPIOF0) Input/ Output D8 29 (GPIOF1 (GPIOF2) D10 32 (GPIOF3) D11 133 (GPIOF4) D12 134 (GPIOF5) D13 135 (GPIOF6) ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type RD 45 Output WR 44 Output PS 46 Output (CS0) (GPIOD8) Input/ Output 24 State During Signal Description Reset In reset, Read Enable — RD ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type DS 47 Output (CS1) (GPIOD9) Input/ Output GPIOD0 48 Input/ Output (CS2) Output (CAN2_TX) Open Drain Output Freescale Semiconductor Preliminary State During Signal Description Reset ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type GPIOD1 49 Schmitt Input/ Output (CS3) Output (CAN2_RX) Schmitt Input TXD0 4 Output (GPIOE0) Input/ Output RXD0 5 Input (GPIOE1) Input/ Output 26 State During ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type TXD1 42 Output (GPIOD6) Input/ Output RXD1 43 Input (GPIOD7) Input/ Output TCK 121 Schmitt Input TMS 122 Schmitt Input TDI 123 Schmitt Input TDO ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type TRST 120 Schmitt Input PHASEA0 139 Schmitt Input (TA0) Schmitt Input/ Output (GPIOC4) Schmitt Input/ Output PHASEB0 140 Schmitt Input (TA1) Schmitt Input/ Output (GPIOC5) ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type INDEX0 141 Schmitt Input (TA2) Schmitt Input/ Output (GPOPC6) Schmitt Input/ Output HOME0 142 Schmitt Input (TA3) Schmitt Input/ Output (GPIOC7) Schmitt Input/ Output SCLK0 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type MOSI0 132 Input/ Output (GPIOE5) Input/ Output MISO0 131 Input/ Output (GPIOE6) Input/ Output SS0 129 Input (GPIOE7) Input/ Output 30 State During Signal Description ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type PHASEA1 6 Schmitt Input (TB0) Schmitt Input/ Output (SCLK1) Schmitt Input/ Output (GPIOC0) Schmitt Input/ Output PHASEB1 7 Schmitt Input (TB1) Schmitt Input/ Output (MOSI1) ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type INDEX1 8 Schmitt Input (TB2) Schmitt Input/ Output (MISO1) Schmitt Input/ Output (GPIOC2) Schmitt Input/ Output HOME1 9 Schmitt Input (TB3) Schmitt Input/ Output (SS1) ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type PWMA0 62 Output PWMA1 64 PWMA2 65 PWMA3 67 PWMA4 68 PWMA5 70 ISA0 113 Schmitt Input (GPIOC8) Schmitt Input/ ISA1 114 Output (GPIOC9) ISA2 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type ISB0 50 Schmitt Input (GPIOD10) Schmitt Input/ ISB1 52 Output (GPIOD11) ISB2 53 (GPIOD12) FAULTB0 56 Schmitt Input FAULTB1 57 FAULTB2 58 FAULTB3 61 ANA0 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type ANB0 104 Input ANB1 105 ANB2 106 ANB3 107 ANB4 108 Input ANB5 109 ANB6 110 ANB7 111 TEMP_SENSE 96 Output CAN_RX 127 Schmitt Input ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type TD0 116 Schmitt Input/ Output (GPIOE10) Schmitt Input/ TD1 117 Output (GPIOE11) IRQA 54 Schmitt Input IRQB 55 RESET 86 Schmitt Input RSTO 85 Output ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type EXTBOOT 112 Schmitt Input EMI_MODE 143 Schmitt Input Freescale Semiconductor Preliminary State During Signal Description Reset Input, External Boot — This input is tied to ...
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Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. specific OCCS ...
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The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL R z CLKMODE ...
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External Clock Source The recommended method of connecting an external clock is given in source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an external clock source as well. Figure 3-4 ...
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Note: Data Flash and Program RAM are NOT available on the 56F8166 device. Table 4-1 Chip Memory Configurations On-Chip Memory 56F8366 Program Flash 512KB Data Flash 32KB Program RAM 4KB Data RAM 32KB Program Boot Flash 32KB 4.2 Program Map ...
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Table 4-3 Changing OMR MA Value During Normal Operation OMR MA 0 Use internal P-space memory map configuration 1 Use external P-space memory map configuration – reset, changing this bit has no effect. The device’s ...
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Note: Program RAM is NOT available on the 56F8166 device. Table 4-4 Program Memory Map at Reset Mode 0 ( Begin/End Internal Boot Address Internal Boot 16-Bit External Address Bus P:$1F FFFF External Program Memory P:$10 0000 P:$0F ...
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Interrupt Vector Table Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority of an interrupt can be ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level PLL FLEXCAN 26 FLEXCAN 27 FLEXCAN 28 FLEXCAN 29 GPIOF 30 GPIOE 31 GPIOD 32 GPIOC 33 GPIOB 34 GPIOA 35 SPI1 ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level TMRC 56 TMRC 57 TMRC 58 TMRC 59 TMRB 60 TMRB 61 TMRB 62 TMRB 63 TMRA 64 TMRA 65 TMRA 66 TMRA 67 SCI0 68 SCI0 69 SCI0 ...
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Data Map Note: Data Flash is NOT available on the 56F8166 device. Begin/End Address X:$FF FFFF EOnCE X:$FF FF00 256 locations allocated X:$FF FEFF External Memory X:$01 0000 X:$00 FFFF On-Chip Peripherals X:$00 F000 4096 locations allocated X:$00 EFFF ...
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Program Memory BOOT_FLASH_START + $3FFF BOOT_FLASH_START = $04_0000 PROG_FLASH_START + $03_FFFF Configure Field PROG_FLASH_START + $02_0000 PROG_FLASH_START + $01_FFFF PROG_FLASH_START = $00_0000 Figure 4-1 Flash Array Memory Maps Table 4-7 shows the page and sector sizes used within each Flash ...
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EOnCE Memory Map Address Register Acronym X:$FF FF8A OESCR X:$FF FF8E OBCNTR X:$FF FF90 OBMSK (32 bits) X:$FF FF91 — X:$FF FF92 OBAR2 (32 bits) X:$FF FF93 — X:$FF FF94 OBAR1 (24 bits) X:$FF FF95 — X:$FF FF96 OBCR ...
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Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be ...
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Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral SIM Power Supervisor FM FlexCAN FlexCAN2 Table 4-10 External Memory Integration Registers Address Map Register Acronym Address Offset CSBAR 0 $0 CSBAR 1 $1 CSBAR 2 $2 CSBAR 3 ...
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Table 4-10 External Memory Integration Registers Address Map (Continued) Register Acronym Address Offset CSOR 1 $9 CSOR 2 $A CSOR 3 $B CSOR 4 $C CSOR 5 $D CSOR 6 $E CSOR 7 $F CSTC 0 $10 CSTC 1 $11 ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSC Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the 56F8166 device Register Acronym TMRB0_CMP1 TMRB0_CMP2 TMRB0_CAP ...
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Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8166 device Register Acronym TMRB1_CMPLD2 TMRB1_COMSCR TMRB2_CMP1 TMRB2_CMP2 TMRB2_CAP TMRB2_LOAD TMRB2_HOLD TMRB2_CNTR TMRB2_CTRL TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR ...
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Table 4-13 Quad Timer C Registers Address Map Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL 56 ...
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Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Table 4-14 Quad Timer D Registers Address Map Quad Timer D is NOT available ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8166 device Register Acronym TMRD1_CMP1 TMRD1_CMP2 TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8166 device Register Acronym TMRD3_CTRL TMRD3_SCR TMRD3_CMPLD1 TMRD3_CMPLD2 TMRD3_COMSCR Table 4-15 Pulse Width Modulator A Registers Address Map PWMA is NOT available in ...
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Table 4-16 Pulse Width Modulator B Registers Address Map Register Acronym PWMB_PMCTL PWMB_PMFCTL PWMB_PMFSA PWMB_PMOUT PWMB_PMCNT PWMB_PWMCM PWMB_PWMVAL0 PWMB_PWMVAL1 PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym ...
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Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued) Register Acronym DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Table 4-18 Quadrature Decoder 1 Registers Address Map Quadrature Decoder 1 is NOT available on the 56F8166 device Register Acronym DEC1_DECCR DEC1_FIR ...
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Table 4-19 Interrupt Control Registers Address Map Register Acronym IPR 0 IPR 1 IPR 2 IPR 3 IPR 4 IPR 5 IPR 6 IPR 7 IPR 8 IPR 9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map Register Acronym ADCA_CR 1 ADCA_CR 2 ADCA_ZCC ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT 4 ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_HLMT 6 ADCA_HLMT 7 ADCA_OFS 0 ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ADCA_OFS 5 ADCA_OFS 6 ADCA_OFS 7 ADCA_POWER ADCA_CAL Table 4-21 Analog-to-Digital Converter Registers Address Map Register ...
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Table 4-21 Analog-to-Digital Converter Registers Address Map (ADCB_BASE = $00 F240) (Continued) Register Acronym ADCB_RSLT 7 ADCB_LLMT 0 ADCB_LLMT 1 ADCB_LLMT 2 ADCB_LLMT 3 ADCB_LLMT 4 ADCB_LLMT 5 ADCB_LLMT 6 ADCB_LLMT 7 ADCB_HLMT 0 ADCB_HLMT 1 ADCB_HLMT 2 ADCB_HLMT 3 ...
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Table 4-22 Temperature Sensor Register Address Map Temperature Sensor is NOT available in the 56F8166 device Register Acronym TSENSOR_CNTL Table 4-23 Serial Communication Interface 0 Registers Address Map Register Acronym SCI0_SCIBR SCI0_SCICR SCI0_SCISR SCI0_SCIDR Table 4-24 Serial Communication Interface 1 ...
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Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Table 4-27 Computer Operating Properly Registers Address Map Register Acronym COPCTL COPTO COPCTR Table 4-28 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB ...
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Table 4-29 GPIOA Registers Address Map Address Offset Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR GPIOA_PPMODE GPIOA_RAWDATA Table 4-30 GPIOB Registers Address Map Register Acronym Address Offset GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR ...
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Table 4-31 GPIOC Registers Address Map Register Acronym Address Offset GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR ...
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Table 4-33 GPIOE Registers Address Map Register Acronym Address Offset GPIOE_PUR GPIOE_DR GPIOE_DDR GPIOE_PER GPIOE_IAR GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR GPIOE_PPMODE GPIOE_RAWDATA Table 4-34 GPIOF Registers Address Map Register Acronym Address Offset GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR ...
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Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL SIM_PCE2 Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Freescale Semiconductor Preliminary (SIM_BASE ...
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Table 4-37 Flash Module Registers Address Map Register Acronym FMCLKD FMMCR FMSECH FMSECL FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8166 device Register Acronym FCMCR ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8166 device Register Acronym FCMAXMB FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8166 device Register Acronym FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB5_CONTROL FCMB5_ID_HIGH ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8166 device Register Acronym FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8166 device Register Acronym FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8166 device Register Acronym FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA Table 4-39 FlexCAN2 Registers Address Map ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8166 device Register Acronym FC2IMASK2 FC2RXGMASK_H FC2RXGMASK_L FC2RX14MASK_H FC2RX14MASK_L FC2RX15MASK_H FC2RX15MASK_L FC2STATUS FC2IMASK1 FC2IFLAG1 FC2R/T_ERROR_CNTRS FC2IFLAG 2 FC2MB0_CONTROL FC2MB0_ID_HIGH FC2MB0_ID_LOW FC2MB0_DATA FC2MB0_DATA FC2MB0_DATA FC2MB0_DATA FC2MSB1_CONTROL FC2MSB1_ID_HIGH FC2MSB1_ID_LOW ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8166 device Register Acronym FC2MB2_CONTROL FC2MB2_ID_HIGH FC2MB2_ID_LOW FC2MB2_DATA FC2MB2_DATA FC2MB2_DATA FC2MB2_DATA FC2MB3_CONTROL FC2MB3_ID_HIGH FC2MB3_ID_LOW FC2MB3_DATA FC2MB3_DATA FC2MB3_DATA FC2MB3_DATA FC2MB4_CONTROL FC2MB4_ID_HIGH FC2MB4_ID_LOW FC2MB4_DATA FC2MB4_DATA FC2MB4_DATA FC2MB4_DATA FC2MB5_CONTROL FC2MB5_ID_HIGH ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8166 device Register Acronym FC2MB6_CONTROL FC2MB6_ID_HIGH FC2MB6_ID_LOW FC2MB6_DATA FC2MB6_DATA FC2MB6_DATA FC2MB6_DATA FC2MB7_CONTROL FC2MB7_ID_HIGH FC2MB7_ID_LOW FC2MB7_DATA FC2MB7_DATA FC2MB7_DATA FC2MB7_DATA FC2MB8_CONTROL FC2MB8_ID_HIGH FC2MB8_ID_LOW FC2MB8_DATA FC2MB8_DATA FC2MB8_DATA FC2MB8_DATA FC2MB9_CONTROL FC2MB9_ID_HIGH ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8166 device Register Acronym FC2MB9_DATA FC2MB10_CONTROL FC2MB10_ID_HIGH FC2MB10_ID_LOW FC2MB10_DATA FC2MB10_DATA FC2MB10_DATA FC2MB10_DATA FC2MB11_CONTROL FC2MB11_ID_HIGH FC2MB11_ID_LOW FC2MB11_DATA FC2MB11_DATA FC2MB11_DATA FC2MB11_DATA FC2MB12_CONTROL FC2MB12_ID_HIGH FC2MB12_ID_LOW FC2MB12_DATA FC2MB12_DATA FC2MB12_DATA FC2MB12_DATA FC2MB13_CONTROL ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8166 device Register Acronym FC2MB13_DATA FC2MB13_DATA FC2MB13_DATA FC2MB14_CONTROL FC2MB14_ID_HIGH FC2MB14_ID_LOW FC2MB14_DATA FC2MB14_DATA FC2MB14_DATA FC2MB14_DATA FC2MB15_CONTROL FC2MB15_ID_HIGH FC2MB15_ID_LOW FC2MB15_DATA FC2MB15_DATA FC2MB15_DATA FC2MB15_DATA 4.8 Factory Programmed Memory The Boot ...
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Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump ...
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Table 5-2 Interrupt Priority Encoding IPIC_LEVEL[1: See IPIC field definition in 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A ...
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Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
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Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has ...
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Add. Register Offset Name IPR0 BKPT_U0 IPL IPR1 IPR2 FMCBE IPL FMCC IPL W R GPIOD GPIOE $3 IPR3 IPL IPR4 ...
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Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0 IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the ...
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Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. ...
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Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ ...
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GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...
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FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...
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Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled ...
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SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Fast Interrupt 0 Match Register (FIM0) Base + $ Read Write RESET Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 Reserved—Bits 15–7 This bit field is reserved or not ...
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Reserved—Bits 15–5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used ...
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Fast Interrupt 1 Vector Address High Register (FIVAH1) Base + $ Read Write RESET Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1) 5.6.17.1 Reserved—Bits 15–5 This bit field ...
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IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for ...
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IRQ Pending 4 Register (IRQP4) Base + $ Read Write RESET Figure 5-24 IRQ Pending 4 Register (IRQP4) 5.6.22.1 IRQ Pending (PENDING)—Bits 80–65 This register combines with the other five to represent the ...
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Reserved —Base + 1B 5.6.29 Reserved —Base + 1C 5.6.30 ITCN Control Register (ICTL) Base + $ Read INT IPIC Write RESET Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This ...
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Reserved—Bit 4 This bit field is reserved or not implemented read as 1 and cannot be modified by writing. 5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3 This read-only bit reflects the state of the external IRQB pin. ...
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FlexCAN2 Message Buffer Interrupt Priority Level (FlexCAN2_MSGBUF IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After ...
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Features The SIM has the following features: • Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory • Power-saving clock gating for peripheral • Three power modes (Run, Wait, Stop) to control power utilization — ...
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Stop Mode When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This ...
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Register Descriptions Address Offset Address Acronym Base + $0 SIM_CONTROL Base + $1 SIM_RSTSTS Base + $2 SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base + $6 SIM_MSH_ID Base + $7 SIM_LSH_ID Base ...
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Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ...
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EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.2.2 Software Reset (SWR)—Bit 5 When 1, this bit indicates that the previous reset occurred as a result ...
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Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the ...
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Reserved —Bit 15 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.2 PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. 6.5.6.3 CAN—Bit 13 This ...
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Reserved—Bit 2–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.7 CLKO Select Register (SIM_CLKOSR) The CLKO select register can be used to multiplex out any one of ...
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Clockout Disable (CLKDIS)—Bit 5 • CLKOUT output is enabled and will output the signal indicated by CLKOSEL • CLKOUT is tri-stated 6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO ...
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Quad Timer Controlled SPI Controlled Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control Table 6-2 Control of GPIOC Pads Using SIM_GPS Control Pin Function GPIO Input 0 GPIO Output 0 Quad Timer Input / 1 Quad Decoder 2 ...
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Two Input/Output pins associated with GPIOD can function as GPIO, EMI (default peripheral) or CAN2 (NOT available in the 56F8166 device) signals. GPIO is the default and is enabled/disabled via the GPIOD_PER, as shown in Figure 6-11 peripheral input/output, then ...
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Base + $ Read Write RESET Figure 6-12 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot ...
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Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip. Base + ...
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Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.7 Quad Timer D Enable ...
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Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.15 Pulse Width ...
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With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents ...
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CAN2 Enable—Bit 0 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.6 Clock Generation Overview The SIM uses ...
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Stop and Wait Mode Disable Function Permanent Disable Reprogrammable Disable Clock Select Figure 6-17 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop ...
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Part 7 Security Features The 56F8366/56F8166 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized ...
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Disabling EOnCE Access On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the ...
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SYS_CLK 2 FM_CLKDIV JTAG FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the ...
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Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access ...
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Table 8-1 56F8366 GPIO Ports Configuration Available GPIO Port Pins in Port Width 56F8366 14 pins - EMI Address pins pin - EMI Address pin pins - EMI Address pins - Not ...
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Table 8-2 56F8166 GPIO Ports Configuration (Continued) Available GPIO Port Pins in Port Width 56F8166 pins - SCI0 2 pins - EMI Address pins 4 pins - SPI0 1 pin - TMRC 1 pin - TMRC ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOB 1 This is a function of the EMI_MODE, EXTBOOT, and Flash ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOD GPIOE Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 GPIO 1 ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOF 1. See Part 6.5.8 to determine how to select peripherals from ...
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Part 10 Specifications 10.1 General Characteristics The 56F8366/56F8166 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up ...
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Note: The 56F8166 device is guaranteed to 40MHz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8166 device. Table 10-1 Absolute Maximum Ratings Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal ...
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Table 10-2 56F8366/56F8166 ElectroStatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection ...
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Note: The 56F8166 device is guaranteed to 40MHz and specified to meed Industrial requirements only; CAN is NOT available on the 56F8166 device. Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic Supply voltage ADC Supply Voltage Oscillator ...
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DC Electrical Characteristics Note: The 56F8166 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8166 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol Output High Voltage V OH ...
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Table 10-6 Power on Reset Low Voltage Parameters Characteristic POR Trip Point 1 LVI, 2.5 volt Supply, trip point 2 LVI, 3.3 volt supply, trip point Bias Current 1. When V drops below V DD_CORE 2. When V drops below ...
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Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 950μA Stop2 100μ Output Switching Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200mA ...
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Characteristics PLL Start-up time Resonator Start-up time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode 10.2.1 Temperature Sensor Note: Temperature Sensor is NOT available in the 56F8166 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain) ...
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AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in ...
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External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) 3 Clock Pulse Width 4 External clock input rise time 5 External clock input fall time 1. Parameters listed are guaranteed ...
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Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Bias Current, low-drive mode ...
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DCAOE and DCAEO are calculated as follows: 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 DCAOE = = 0.0 all other cases MIN XTAL duty cycle - 0.5, if ...
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Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted Valid Data Out Hold Time after WR Deasserted Valid Data Out Set Up Time to WR ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration RESET Deassertion to First External Address ...
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IRQA, IRQB Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive) A0–A15 t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 10-7 External Level-Sensitive Interrupt Timing IRQA, IRQB A0–A15 Figure 10-8 Interrupt from Wait State Timing ...
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IW IRQA A0–A15 Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 10.10 Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master ...
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Characteristic Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 10-10 SPI Master ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-11 SPI Master Timing (CPHA = 1) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-13 SPI Slave Timing (CPHA = 1) 10.11 Quad Timer Timing Characteristic Timer input period Timer input high / low period ...
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Timer Inputs Timer Outputs 10.12 Quadrature Decoder Timing Table 10-20 Quadrature Decoder Timing Characteristic Quadrature input period Quadrature input high / low period Quadrature phase period 1. In the formulas listed the clock cycle. For 60MHz operation, T ...
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Serial Communication Interface (SCI) Timing Characteristic Symbol 2 Baud Rate 3 RXD RXD Pulse Width 4 TXD TXD Pulse Width 1. Parameters listed are guaranteed by design the frequency of operation of the system clock, ZCLK, ...
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CAN_RX CAN receive data pin (Input) Figure 10-18 Bus Wake Up Detection 10.15 JTAG Timing Characteristic TCK frequency of operation 1 using EOnCE TCK frequency of operation not 1 using EOnCE TCK clock pulse width TMS, TDI data set-up time ...
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TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-20 Test Access Port Timing Diagram TRST (Input) 10.16 Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion ...
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Table 10-24 ADC Parameters (Continued) Characteristic ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection current , per pin Input injection current, total V current REFH ADC A current ADC B current Quiescent current Uncalibrated ...
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Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken ...
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Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & open, one ...
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C, the internal [dynamic component], is classic C*V 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly ...
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Part 11 Packaging 11.1 56F8366 Package and Pin-Out Information This section contains package and pin-out information for the 56F8366. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP). shows the mechanical parameters for this package, and Orientation Mark ...
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Table 11-1 56F8366 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO CLKO 39 4 TXD0 40 5 RXD0 41 6 PHASEA1 42 7 PHASEB1 43 ...
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Table 11-1 56F8366 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name 25 A14 61 26 A15 DD_IO 32 ...
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Package and Pin-Out Information This section contains package and pin-out information for the 56F8166. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP). shows the mechanical parameters for this package, and Orientation Mark V DD_IO V ...
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Table 11-2 56F8166 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO CLKO 39 4 TXD0 40 5 RXD0 41 6 SCLK1 42 7 MOSI1 43 ...
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Table 11-2 56F8166 144-Pin LQFP Package Identification by Pin Number (Continued) Signal Pin No. Pin No. Name 26 A15 DD_IO 32 D10 68 ...
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H B 144 PIN 1 INDEX D1/2 D TOP VIEW H A SIDE VIEW PLATING BASE b METAL 0. SECTION A-A ° ...
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Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature θJΑ where Ambient temperature for the package ( ...
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The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small ...
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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and V circuits. DD ...
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... Technical Data, Rev. 6 Ambient Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8366VFV60 60 -40° 125° C MC56F8366MFV60 40 -40° 105° C MC56F8166VFV 60 -40° 105° C MC56F8366VFVE* 60 -40° 125° C MC56F8366MFVE* 40 -40° 105° C MC56F8166VFVE* ...
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Freescale Semiconductor Preliminary 56F8366 Technical Data, Rev. 6 Power Distribution and I/O Ring Implementation 181 ...
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Technical Data, Rev. 6 Freescale Semiconductor Preliminary ...
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Freescale Semiconductor Preliminary 56F8366 Technical Data, Rev. 6 Power Distribution and I/O Ring Implementation 183 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8366 Rev. 6 01/2007 ...